SLES102B December   2003  – March 2015 PCM1798

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics for Digital Filter
      1. 6.7.1 Analog Dynamic Performance
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Clock and Reset Functions
        1. 7.3.1.1 System Clock Input
      2. 7.3.2 Power-On and External Reset Functions
      3. 7.3.3 Audio Data Interface
        1. 7.3.3.1 Audio Serial Interface
        2. 7.3.3.2 PCM Audio Data Formats and Timing
      4. 7.3.4 Function Descriptions
        1. 7.3.4.1 Audio Data Format
        2. 7.3.4.2 Soft Mute
        3. 7.3.4.3 De-Emphasis
        4. 7.3.4.4 Zero Detection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application for External Digital Filter Interface
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Application for Interfacing With an External Digital Filter
          2. 8.2.1.2.2 Audio Format
          3. 8.2.1.2.3 Analog Output
        3. 8.2.1.3 Application Curves
      2. 8.2.2 PCM1798 Typical Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 I/V Section
          2. 8.2.2.2.2 Differential Section
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
  • DB|28
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The PCM1798 is a 24-bit, 192-kHz, differential current output DAC that comes in a 28-pin SSOP package. The PCM1798 is a hardware controlled and utilizes the advanced segment DAC architecture from TI in order to perform with a Stereo Dynamic Range of 123 dB (126 dB Mono) and SNR of 123 dB (126 dB Mono) with a THD of 0.0005%. The PCM1798 will use the SCK input as its system clock and automatically detect the sampling rate of the Digital Audio input and has a high tolerance for clock jitter. The internal filter can be bypassed to allow for an external digital filter to be used.

7.2 Functional Block Diagram

PCM1798 fbd_sles102.gif

7.3 Feature Description

7.3.1 System Clock and Reset Functions

7.3.1.1 System Clock Input

The PCM1798 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1798 has a system clock detection circuit that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system clock frequencies for common audio sampling rates.

Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators is an excellent choice for providing the PCM1798 system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
128 fS 192 fS 256 fS 384 fS 512 fS 768 fS
32 kHz 4.096 6.144 8.192 12.288 16.384 24.576
44.1 kHz 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688
48 kHz 6.144 9.216 12.288 18.432 24.576 36.864
96 kHz 12.288 18.432 24.576 36.864 49.152 73.728
192 kHz 24.576 36.864 49.152 73.728 See(1) See(1)
(1) This system clock rate is not supported for the given sampling frequency.

7.3.2 Power-On and External Reset Functions

The PCM1798 includes a power-on reset function. Figure 2 shows the operation of this function. With VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V.

The PCM1798 also includes an external reset capability using the RST input (pin 14). This allows an external controller or master reset circuit to force the PCM1798 to initialize to its default reset state.

Figure 3 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The external reset is especially useful in applications where there is a delay between the PCM1798 power up and system clock activation.

7.3.3 Audio Data Interface

7.3.3.1 Audio Serial Interface

The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1798 on the rising edge of BCK. LRCK is the serial audio left/right word clock.

The PCM1798 requires the synchronization of LRCK and the system clock, but does not need a specific phase relation between LRCK and the system clock.

If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is initialized within 1/fS and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the system clock is completed.

7.3.3.2 PCM Audio Data Formats and Timing

The PCM1798 supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified. The data formats are shown in Figure 5, Figure 6, and Figure 7. Data formats are selected using FMT0 (pin 11) and FMT1 (pin 12) as shown in Table 2. All formats require binary twos-complement, MSB-first audio data. Figure 4 shows a detailed timing diagram for the serial audio interface.

7.3.4 Function Descriptions

7.3.4.1 Audio Data Format

Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1798 also supports monaural mode and DF bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1798 can select the DF rolloff characteristics.

Table 2. Audio Data Format Select

MONO CHSL FMT1 FMT0 FORMAT STEREO/MONO DF ROLLOFF
0 0 0 0 I2S Stereo Sharp
0 0 0 1 Left-justified format Stereo Sharp
0 0 1 0 Standard, 16-bit Stereo Sharp
0 0 1 1 Standard, 24-bit Stereo Sharp
0 1 0 0 I2S Stereo Slow
0 1 0 1 Left-justified format Stereo Slow
0 1 1 0 Standard, 16-bit Stereo Slow
0 1 1 1 Digital filter bypass Mono —
1 0 0 0 I2S Mono, L-channel Sharp
1 0 0 1 Left-justified format Mono, L-channel Sharp
1 0 1 0 Standard, 16-bit Mono, L-channel Sharp
1 0 1 1 Standard, 24-bit Mono, L-channel Sharp
1 1 0 0 I2S Mono, R-channel Sharp
1 1 0 1 Left-justified format Mono, R-channel Sharp
1 1 1 0 Standard, 16-bit Mono, R-channel Sharp
1 1 1 1 Standard, 24-bit Mono, R-channel Sharp

7.3.4.2 Soft Mute

The PCM1798 supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs are transitioned to the bipolar zero level in –0.5-dB steps with a transition speed of 1/fS per step. This system provides pop-free muting of the DAC output.

7.3.4.3 De-Emphasis

The PCM1798 has a de-emphasis filter for the sampling frequency of 44.1 kHz. The de-emphasis filter is controlled using DEM (pin 3).

7.3.4.4 Zero Detection

When the PCM1798 detects that the audio input data in the L-channel and the R-channel is continuously zero for 1024 LRCKs in the PCM mode, or that the audio input data is continuously zero for 1024 WDCKs in the external filter mode, the PCM1798 sets ZERO (pin 13) to HIGH.

7.4 Device Functional Modes

The PCM1798 is a hardware controlled device. The pins CHSL, DEM, FMT0, FMT1, MONO, and MUTE control the functionality of this part. See the Pin Functions table or the Feature Description section for more detail.