SLASE64A December 2014 – June 2017 PCM1860-Q1 , PCM1861-Q1 , PCM1862-Q1 , PCM1863-Q1 , PCM1864-Q1 , PCM1865-Q1
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The PCM186x-Q1 family is extremely flexible, and this flexibility gives rise to a number of design questions that define the design requirements for a given application.
In this section, the design choices are described, followed by a typical system implementation. The simplified application diagrams shown in Figure 64 and Figure 66 illustrate a typical system that would require the following architecture decisions to be made:
An example application diagram is shown in Figure 54.
The PCM1860-Q1 and PCM1861-Q1 are controlled with pullup or pulldown voltages on pins MD0 through MD6. The INT pin is ideally designed to be used with a microcontroller that can treat the pin as both an input (when used as an interrupt) and as an output to pull the pin high, and force power down. See the Pin Configuration and Functions for the PCM1860-Q1 and PCM1861-Q1 for specific configuration details. The hardware control interface is shown in Figure 55.
SPI control is selected by the MD0 pin; in this case, MDO connects to 3.3 V, so that the device acts as an SPI slave. The SPI control interface is shown in Figure 56.
I2C control is selected by the MD0 pin; in this example, MDO is pulled down to ground, so that the device acts as an I2C slave. One address line is supported to select between two devices on the same bus. The I2C control interface is shown in Figure 57.
The 3.3-V AVDD, DVDD, and IOVDD Example is the most typical power-supply configuration. The 3.3-V single supply is shown in Figure 58.
For details regarding lower-power applications, see 3.3-V AVDD, DVDD With 1.8-V IOVDD Example for Lower-Power Applications for lower-power applications.
The PCM186x-Q1 family offers three different clock sources. For the highest performance, run the ADC in master mode from a stable, well-known SCK source, such as a CMOS SCK, or a external crystal (XTAL). The PCM186x-Q1 is easy to hook up to a crystal, simply connect to XI and XO, and add capacitors to ground, as suggested in the XTAL manufacturer's data sheet (typically 15 pF).
External CMOS clock sources can be brought directly into the SCKI pin (for 3.3-V sources) or into the XI pin (1.8 V sources).
The PLL must be enabled if the clock source is unrelated to the audio rate. For instance, a 12-MHz USB crystal requires custom PLL settings to generate the 48-kHz rate clocks and the 44.1-kHz rate clocks required by many audio systems. An example with a 12-MHz clock is shown in Software-Controlled Devices Manual PLL Calculation.
For timing limits on XTAL and SCKI, see the Specifications section.
Two PCM186x-Q1 software-controlled devices can be used together to create an 8-channel (or higher) channel count system using a TDM. In Figure 59, Device A is used as the TDM clock master, and Device B is configured to be a TDM slave and transmit on channels 5, 6, 7, and 8 of the TDM stream. The key difference is that Device A most likely has a crystal, or an SCKI source, and is configured to be the TDM master, whereas Device B does not require an XTAL or SCKI source because Device B uses the internal PLL to generate the required system clocks. Another two channels can be added to the stream from a stereo device; however, I2C address management is required because the PCM186x-Q1 software-controlled devices can only have one of two I2C addresses.
Most systems can simply use an input filter similar to the one shown in Figure 60. However, for systems with significant out-of-band noise, a simple filter such as that shown in Figure 61 can be used for pre-ADC, antialiasing filtering. The recommended resistor value for the antialiasing filter is 100 Ω. Place film-type capacitors of 0.01 µF as close as possible to the VINLx and VINRx pins, and terminate to GND as close as possible to the AGND pin in order to maximize the dynamic performance of the ADC.
Adding this filter resistor also adds some input current limiting into the device, if the ESD diodes begin to clamp the signal when the maximum input voltage is exceeded. Keep the current through the input ESD diodes as low as possible, with ~5 mA treated as a absolute maximum. Any higher and the ESD diodes may fail because of the thermal constraints.
As in single-ended applications, most systems can simply use an input filter similar to Figure 62. However, for systems with significant out-of-band noise, a simple filter such as that shown in Figure 63 can be used for pre-ADC, antialiasing filtering. The recommended resistor value for the antialiasing filter is 47 Ω. Place film-type capacitors of 0.01 µF as close as possible to the VINLx and VINRx pins, and terminate to GND as close as possible to the AGND pin in order to maximize the dynamic performance of ADC. To maintain common-mode rejection, match the series resistors as closely as possible.