SBAS452A September   2008  – January 2016 PCM3168A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Requirements: System Clock
    7. 8.7  Timing Requirements: Power-On Reset
    8. 8.8  Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Slave Mode)
    9. 8.9  Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Master Mode)
    10. 8.10 Timing Requirements: Audio Interface for DSP and TDM (Slave Mode)
    11. 8.11 Timing Requirements: Audio Interface for DSP and TDM (Master Mode)
    12. 8.12 Timing Requirements: DAC Outputs and ADC Outputs
    13. 8.13 Timing Requirements: Four-Wire Serial Control Interface
    14. 8.14 Timing Requirements: SCL and SDA Control Interface
    15. 8.15 Typical Characteristics
      1. 8.15.1 ADC Digital Filter
      2. 8.15.2 DAC Digital Filter
      3. 8.15.3 ADC Performance
      4. 8.15.4 DAC Performance
      5. 8.15.5 Output Spectrum
      6. 8.15.6 Power-Supply
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
      2. 9.3.2  Analog Outputs
      3. 9.3.3  Voltage References
      4. 9.3.4  System Clock Input
      5. 9.3.5  Sampling Mode
      6. 9.3.6  Reset Operation
      7. 9.3.7  Highpass Filter (HPF)
      8. 9.3.8  Overflow Flag
      9. 9.3.9  Zero Flag
      10. 9.3.10 Four-Wire (SPI) Serial Control
      11. 9.3.11 Control Data Word Format
      12. 9.3.12 Register Write Operation
      13. 9.3.13 Register Read Operation
      14. 9.3.14 Two-Wire (I2C) Serial Control
      15. 9.3.15 Packet Protocol
      16. 9.3.16 Write Operation
      17. 9.3.17 Read Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Mode Control
      2. 9.4.2 Hardware Control Mode Configuration
      3. 9.4.3 Audio Serial Port Operation
      4. 9.4.4 Audio Data Interface Formats and Timing
      5. 9.4.5 Synchronization With the Digital Audio System
    5. 9.5 Register Maps
      1. 9.5.1 Control Register Definitions (Software Mode Only)
      2. 9.5.2 Register Definitions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Analog Input and Output
        2. 10.2.2.2 PCM Interface
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Typical Circuit Connections
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  Power-Supply Pins (VCCAD1/2, VCCDA1/2, and VDD1/2)
      2. 12.1.2  Grounding (AGNDAD1/2, AGNDDA1/2, and DGND1/2)
      3. 12.1.3  VIN1±, VIN2±, VIN3±, VIN4±, VIN5±, and VIN6± Pins
      4. 12.1.4  VCOMAD and VCOMDA Pins
      5. 12.1.5  VREFAD1/2 Pins
      6. 12.1.6  VOUT1±, VOU2±, VOUT3±, VOUT4±, VOUT5±, VOUT6±, VOUT7±, and VOUT8± Pins
      7. 12.1.7  MODE Pin
      8. 12.1.8  RST Pin
      9. 12.1.9  OVF Pin
      10. 12.1.10 System Clock and Audio Interface Clocks
      11. 12.1.11 PowerPAD
      12. 12.1.12 External Mute Control
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

A typical circuit connection for six-channel analog in and eight-channel analog out is shown in Figure 54.

10.2 Typical Application

PCM3168A ai_basic_bas452.gif

NOINDENT:

C1 through C6 are 1-μF ceramic capacitors dependent on power-supply quality. C7 and C8 are 10-μF electrolytic capacitors dependent on power-supply quality. C9 and C10 are 10-μF electrolytic capacitors. C11 and C12 are 10-μF electrolytic capacitors. R1 through R12 are 22-Ω to 100-Ω resistors.
Figure 54. Example Board Layout

10.2.1 Design Requirements

For this design example, use the parameters listed in Table 14.

Table 14. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Audio input PCM audio, differential analog audio
Audio output PCM audio, differential analog audio
Control I2C, SPI

10.2.2 Detailed Design Procedure

10.2.2.1 Analog Input and Output

It is recommended that input and output filters be used to condition the inputs and outputs. Input filters can be used to convert a single ended signal into a differential signal while also attenuating out of band noise. Another use of an input filter for the ADC it to reduce a 2-VRMS signal to a 1-VRMS input, which is the limit of the ADC input. Output filters can be used to go from differential to single ended, while reducing a differential signal that is 8 VPP to a 2-VRMS signal. The output filter can also attenuate out of band noise.

10.2.2.2 PCM Interface

The PCM3168A has the capability of inputting 8 PCM channels over 4 data pins in normal PCM mode, or can operate in TDM mode to take in 8 channels on one data pin. The PCM3168A can also output up to 6 PCM channels over 3 data pins, or over 1 pin in TDM mode.

10.2.3 Application Curves

PCM3168A tc_adc_out_spec1_bas452.gif
–1 dB, N = 32768
Figure 55. ADC Output Spectrum
PCM3168A tc_dac_out_spec0_bas452.gif
0 dB, N = 32768
Figure 56. DAC Output Spectrum

10.3 System Examples

10.3.1 Typical Circuit Connections

Termination for mode control: Any one of the circuits shown in Figure 57 must be applied according to the necessary mode or configuration. Resistor value must be 220-kΩ, ±5% tolerant. The PowerPAD must be tied to the ground plane with enough electrical and thermal conductivity; see the example board layout in Figure 54.

PCM3168A ai_typ_connex_bas452.gif Figure 57. Typical Circuit Connections

Typical interface circuits for analog input and analog output are shown in Figure 58 through Figure 62.

PCM3168A ai_s2d_buf_4amp_bas452.gif

NOINDENT:

Amplifier is an NE5532A x2 or OPA2134 x2; R1 = 1.5-kΩ resistor; R2 = 750-Ω resistor; R3 = 47-Ω resistor; C1 = 3300-pF capacitor; C2 = 0.01-μF capacitor; Gain = 1; f–3 dB = 45 kHz.
Figure 58. Single-Ended to Differential Buffer and Anti-Aliasing LPF For Differential ADC Input

PCM3168A ai_buf_lpf_1end_adc_bas452.gif

NOINDENT:

Amplifier is an NE5532A x1 or OPA2134 x1; R1 = 3-kΩ resistor; R2 = 1.5-kΩ resistor; R3 = 47-Ω resistor; C1 = 2200-pF capacitor; C2 = 0.022-μF capacitor; Gain = 0.5; f–3 dB = 48 kHz.
Figure 60. Buffer and Anti-Aliasing LPF for Single-Ended ADC Input
PCM3168A ai_post_lpf_dc_bas452.gif

NOINDENT:

Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R1 = 15-kΩ resistor; R2 = 11-kΩ resistor; R3 = 820-Ω resistor; C1 = 1500-pF capacitor; C2 = 330-pF capacitor; Gain = 0.733; f–3 dB = 54 kHz.
Figure 62. Post-LPF and Differential to Single-Ended Buffer for DAC Output (DC-Coupled)
PCM3168A ai_s2d_buf_2amp_bas452.gif

NOINDENT:

Amplifier is an NE5532A x1 or OPA2134 x1; R1 = 3-kΩ resistor; R2 = 1.5-kΩ resistor; R3 = 47-Ω resistor; C1 = 2200-pF capacitor; C2 = 0.01-μF capacitor; Gain = 1; f–3 dB = 48 kHz.
Figure 59. Single-Ended to Differential Buffer and Anti-Aliasing LPF For Differential ADC Input

PCM3168A ai_post_lpf_ac_bas452.gif

NOINDENT:

Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R1 = 7.5-kΩ resistor; R2 = 5.6-kΩ resistor; R3 = 360-Ω resistor; C1 = 3300-pF capacitor; C2 = 680-pF capacitor; Gain = 0.747; f–3 dB = 53 kHz.
Figure 61. Post-LPF and Differential to Single-Ended Buffer for DAC Output (AC-Coupled)
PCM3168A ai_dif_in_cir_lpf_bas452.gif Figure 63. Basic Differential Input Circuit With Anti-Aliasing LPF for Differential ADC Input