SBAS452A September   2008  – January 2016 PCM3168A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Requirements: System Clock
    7. 8.7  Timing Requirements: Power-On Reset
    8. 8.8  Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Slave Mode)
    9. 8.9  Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Master Mode)
    10. 8.10 Timing Requirements: Audio Interface for DSP and TDM (Slave Mode)
    11. 8.11 Timing Requirements: Audio Interface for DSP and TDM (Master Mode)
    12. 8.12 Timing Requirements: DAC Outputs and ADC Outputs
    13. 8.13 Timing Requirements: Four-Wire Serial Control Interface
    14. 8.14 Timing Requirements: SCL and SDA Control Interface
    15. 8.15 Typical Characteristics
      1. 8.15.1 ADC Digital Filter
      2. 8.15.2 DAC Digital Filter
      3. 8.15.3 ADC Performance
      4. 8.15.4 DAC Performance
      5. 8.15.5 Output Spectrum
      6. 8.15.6 Power-Supply
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
      2. 9.3.2  Analog Outputs
      3. 9.3.3  Voltage References
      4. 9.3.4  System Clock Input
      5. 9.3.5  Sampling Mode
      6. 9.3.6  Reset Operation
      7. 9.3.7  Highpass Filter (HPF)
      8. 9.3.8  Overflow Flag
      9. 9.3.9  Zero Flag
      10. 9.3.10 Four-Wire (SPI) Serial Control
      11. 9.3.11 Control Data Word Format
      12. 9.3.12 Register Write Operation
      13. 9.3.13 Register Read Operation
      14. 9.3.14 Two-Wire (I2C) Serial Control
      15. 9.3.15 Packet Protocol
      16. 9.3.16 Write Operation
      17. 9.3.17 Read Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Mode Control
      2. 9.4.2 Hardware Control Mode Configuration
      3. 9.4.3 Audio Serial Port Operation
      4. 9.4.4 Audio Data Interface Formats and Timing
      5. 9.4.5 Synchronization With the Digital Audio System
    5. 9.5 Register Maps
      1. 9.5.1 Control Register Definitions (Software Mode Only)
      2. 9.5.2 Register Definitions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Analog Input and Output
        2. 10.2.2.2 PCM Interface
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Typical Circuit Connections
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  Power-Supply Pins (VCCAD1/2, VCCDA1/2, and VDD1/2)
      2. 12.1.2  Grounding (AGNDAD1/2, AGNDDA1/2, and DGND1/2)
      3. 12.1.3  VIN1±, VIN2±, VIN3±, VIN4±, VIN5±, and VIN6± Pins
      4. 12.1.4  VCOMAD and VCOMDA Pins
      5. 12.1.5  VREFAD1/2 Pins
      6. 12.1.6  VOUT1±, VOU2±, VOUT3±, VOUT4±, VOUT5±, VOUT6±, VOUT7±, and VOUT8± Pins
      7. 12.1.7  MODE Pin
      8. 12.1.8  RST Pin
      9. 12.1.9  OVF Pin
      10. 12.1.10 System Clock and Audio Interface Clocks
      11. 12.1.11 PowerPAD
      12. 12.1.12 External Mute Control
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

PAP Package
64-Pin HTQFP With PowerPAD
Top View
PCM3168A po_bas452.gif

Pin Functions

PIN I/O PULL-DOWN 5-V TOLERANT DESCRIPTION
NO. NAME
1 VCOMAD — No No ADC analog common voltage decoupling
2 AGNDAD2 — No No Analog ground 2 for ADC
3 VCCAD2 — No No ADC analog power supply 2, 5 V
4 RST I Yes Yes Reset and power-down control input with active low
5 OVF O No No Overflow flag output for ADC
6 LRCKAD I/O Yes No Audio data word clock input/output for ADC
7 BCKAD I/O Yes No Audio data bit clock input/output for ADC
8 DOUT1 O No No Audio data digital output for ADC1 and ADC2
9 DOUT2 O No No Audio data digital output for ADC3 and ADC4
10 DOUT3 O No No Audio data digital output for ADC5 and ADC6
11 DGND2 — No No Digital ground 2
12 VDD2 — No No Digital power supply 2, 3.3 V
13 ZERO O No No Zero detect flag output for DAC
14 VCCDA1 — No No DAC analog power supply 1, 5 V
15 VCOMDA — No No DAC voltage common decoupling
16 AGNDDA1 — No No Analog ground 1 for DAC
17 VOUT8+ O No No Positive analog output from DAC8
18 VOUT8– O No No Negative analog output from DAC8
19 VOUT7+ O No No Positive analog output from DAC7
20 VOUT7– O No No Negative analog output from DAC7
21 VOUT6+ O No No Positive analog output from DAC6
22 VOUT6– O No No Negative analog output from DAC6
23 VOUT5+ O No No Positive analog output from DAC5
24 VOUT5– O No No Negative analog output from DAC5
25 VOUT4+ O No No Positive analog output from DAC4
26 VOUT4– O No No Negative analog output from DAC4
27 VOUT3+ O No No Positive analog output from DAC3
28 VOUT3– O No No Negative analog output from DAC3
29 VOUT2+ O No No Positive analog output from DAC2
30 VOUT2– O No No Negative analog output from DAC2
31 VOUT1+ O No No Positive analog output from DAC1
32 VOUT1– O No No Negative analog output from DAC1
33 AGNDDA2 — No No Analog ground 2 for DAC
34 VCCDA2 — No No DAC analog power supply 2, 5 V
35 LRCKDA I/O Yes No Audio data word clock input/output for DAC
36 BCKDA I/O Yes No Audio data bit clock input/output for DAC
37 DIN1 I No No Audio data input for DAC1 and DAC2
38 DIN2 I No No Audio data input for DAC3 and DAC4
39 DIN3 I No No Audio data input for DAC5 and DAC6
40 DIN4 I No No Audio data Input for DAC7 and DAC8
41 SCKI I No Yes System clock input
42 MC/SCL/FMT I No Yes Clock for SPI, clock for I2C, format select for hardware control mode
43 MDI/SDA/DEMP I/O No Yes Input data for SPI, data for I2C(1), de-emphasis control for hardware control mode
44 MDO/ADR1/MD1 I/O No No Output data for SPI(2), address select 1 for I2C, mode select 1 for hardware control mode
45 MS/ADR0/MD0 I Yes Yes Chip select for SPI, address select 0 for I2C, mode select 0 for hardware control mode
46 VDD1 — No No Digital power supply 1, 3.3 V
47 DGND1 — No No Digital ground 1
48 MODE I No No Control port mode selection. Tied to VDD: SPI, pull-up: H/W single-ended input, pull-down: H/W and differential input, tied to DGND: I2C
49 VCCAD1 — No No ADC analog power supply 1, 5 V
50 AGNDAD1 — No No Analog ground 1 for ADC
51 VIN1– I No No Negative analog input to ADC1
52 VIN1+ I No No Positive analog input to ADC1
53 VIN2– I No No Negative analog input to ADC2
54 VIN2+ I No No Positive analog input to ADC2
55 VIN3– I No No Negative analog input to ADC3
56 VIN3+ I No No Positive analog input to ADC3
57 VIN4– I No No Negative analog input to ADC4
58 VIN4+ I No No Positive analog input to ADC4
59 VREFAD1 — No No ADC analog reference voltage 1 decoupling
60 VREFAD2 — No No ADC analog reference voltage 2 decoupling
61 VIN5– I No No Negative analog input to ADC5
62 VIN5+ I No No Positive analog input to ADC5
63 VIN6– I No No Negative analog input to ADC6
64 VIN6+ I No No Positive analog input to ADC6
(1) Open-drain configuration in I2C.
(2) 3-state (Hi-Z) operation in SPI.