PCM514x 2-VRMS DirectPath™, 112/106-dB Audio Stereo DAC With 32-bit, 384-kHz PCM Interface

1 Features

• Programmable miniDSP
• Market-Leading Low Out-of-Band Noise
• Selectable Digital-Filter Latency and Performance
• No DC Blocking Capacitors Required
• Integrated Negative Charge Pump
• Intelligent Muting System; Soft Up or Down Ramp and Analog Mute For 120-dB Mute SNR
• Integrated High-Performance Audio PLL With BCK Reference To Generate SCK Internally
• Accepts 16-, 20-, 24-, And 32-Bit Audio Data
• PCM Data Formats: I²S, Left-Justified, Right-Justified, TDM / DSP
• SPI or I²C Control
• Software or Hardware Configuration
• Automatic Power-Save Mode When LRCK And BCK Are Deactivated
• 1.8-V or 3.3-V Fail-Safe LVCMOS Digital Inputs
• Single Supply Operation:
  3.3-V Analog, 1.8-V or 3.3-V Digital
• Integrated Power-On Reset
• Small 28-pin TSSOP Package

2 Applications

• A/V Receivers
• DVD, BD Players
• HDTV Receivers
• Applications Requiring 2-V_RMS Audio Output

3 Description

The PCM514x devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM514x uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Members of the PCM514x family integrate a fully programmable miniDSP core, allowing developers to integrate filters, dynamic range controls, custom interpolators, and other differentiating features to their products.

The PCM514x provides 2.1-V_RMS ground centered outputs, allowing designers to eliminate DC-blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump-based line drivers by supporting loads down to 1 kΩ, allowing the PCM514x to drive up to 10 products in parallel, such as LCD TV, DVDR, and AV receivers.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I²S connection and reducing system EMI.

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Simplified System Diagram

4 Revision History

Changes from A Revision (September 2012) to B Revision

• Deleted Internal Pop-Free Control For Sample-Rate Changes Or Clock Halts, ... With Popless OperationGo
• Changed Accepts 16-, 24-, And 32-Bit Audio Data to Accepts 16-, 20-, 24-, And 32-Bit Audio DataGo
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
• Clarified Pin Functions table.Go
• Changed Operating temperature to Operating junction temperature in Absolute Maximum RatingsGo
• Deleted redundant PLL specification in Recommended Operating Conditions Go
• Deleted Intelligent clock error... and ...for pop-free performance in the Overview section.Go
• Added note on instruction cycles to PCM512x Audio Processing.Go
• Deleted text The Graphical Development Environment consists of number of Hybrid Flows that can be downloaded to the device and run on the miniDSP. From: Software Go
• Added note on instruction cycles in Fixed Audio Processing Flow (Program 5).Go
• Changed Ouptut to OutputGo
• Deleted VREF mode provides 2.1V_rms full-scale output at both AVDD levels.Go
• Clarified clock generation explanation in Reset and System Clock FunctionsGo
• Clarified external SCK discussion in Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM).Go
• Deleted The PCM514x disables the internal PLL when an external SCK is supplied.Go

5 Device Comparison