SLASE63
November 2014
PCM5252
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
6.1
Control Mode Effect On Pin Assignments
6.2
Pin Assignments
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Switching Characteristics
7.7
Timing Requirements: SCK Input
7.8
Timing Requirements: PCM Audio Data
7.9
Timing Requirements: I2S Master, See
7.10
Timing Requirements: XSMT
7.11
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Terminology
8.3.2
Audio Data Interface
8.3.2.1
Audio Serial Interface
8.3.2.2
PCM Audio Data Formats
8.3.2.3
Zero Data Detect
8.3.3
XSMT Pin (Soft Mute / Soft Un-Mute)
8.3.4
Audio Processing
8.3.4.1
PCM5252 Audio Processing Options
8.3.4.1.1
Overview
8.3.4.1.2
miniDSP Instruction Register
8.3.4.1.3
Digital Output
8.3.4.1.4
Software
8.3.4.2
Interpolation Filter
8.3.4.3
Overview
8.3.4.4
Smart SOA
8.3.4.5
Smart BASS
8.3.4.6
Smart Protection
8.3.4.7
Implementing a Real World Design
8.3.4.8
Digital Output
8.3.4.9
Software
8.3.4.10
Process Flow
8.3.5
DAC and Differential Analog Outputs
8.3.5.1
Analog Outputs
8.3.5.2
Choosing Between VREF and VCOM Modes
8.3.5.2.1
Voltage Reference and Output Levels
8.3.5.2.2
Mode Switching Sequence, from VREF Mode to VCOM Mode
8.3.5.3
Digital Volume Control
8.3.5.3.1
Emergency Ramp-Down
8.3.5.4
Analog Gain Control
8.3.6
Reset and System Clock Functions
8.3.6.1
Clocking Overview
8.3.6.2
Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
8.3.6.3
Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
8.3.6.4
Clock Generation Using the PLL
8.3.6.5
PLL Calculation
8.3.6.5.1
Examples:
8.3.6.5.1.1
Recommended PLL Settings
8.3.6.6
Clock Master Mode from Audio Rate Master Clock
8.3.6.7
Clock Master from a Non-Audio Rate Master Clock
8.4
Device Functional Modes
8.4.1
Choosing a Control Mode
8.4.1.1
Software Control
8.4.1.1.1
SPI Interface
8.4.1.1.1.1
Register Read and Write Operation
8.4.1.1.2
I2C Interface
8.4.1.1.2.1
Slave Address
8.4.1.1.2.2
Register Address Auto-Increment Mode
8.4.1.1.2.3
Packet Protocol
8.4.1.1.2.4
Write Register
8.4.1.1.2.5
Read Register
8.4.1.1.2.6
Timing Characteristics
8.4.2
VREF and VCOM Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
High Fidelity Smartphone Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Initialization Script
9.2.1.3
Application Performance Plot
10
Power Supply Recommendations
10.1
Power Supply Distribution and Requirements
10.2
Recommended Powerdown Sequence
10.2.1
XSMT = 0
10.2.2
Clock Error Detect
10.2.3
Planned Shutdown
10.2.4
Unplanned Shutdown
10.3
External Power Sense Undervoltage Protection Mode
10.4
Power-On Reset Function
10.4.1
Power-On Reset, DVDD 3.3-V Supply
10.4.2
Power-On Reset, DVDD 1.8-V Supply
10.5
PCM5252 Power Modes
10.5.1
Setting Digital Power Supplies and I/O Voltage Rails
13.2.2
PLL Tables for Software Controlled Devices
10.5.2
Power Save Modes
13.2.1.3
Page 1 Registers
13.2.1.3.1
Page 1 / Register 1
13.2.1.3.2
Page 1 / Register 2
13.2.1.3.3
Page 1 / Register 5
13.2.1.3.4
Page 1 / Register 6
13.2.1.3.5
Page 1 / Register 7
13.2.1.3.6
Page 1 / Register 8
13.2.1.3.7
Page 1 / Register 9
13.2.1.4
Page 44 Registers
13.2.1.4.1
Page 44 / Register 1
13.2.1.5
Page 253 Registers
13.2.1.5.1
Page 253 / Register 63
13.2.1.5.2
Page 253 / Register 64
10.5.3
Power Save Parameter Programming
11
Layout
11.1
Layout Guidelines
13.2.1.2.19
Page 0 / Register 24
13.2.1.2.20
Page 0 / Register 27
13.2.1.2.21
Page 0 / Register 28
13.2.1.2.22
Page 0 / Register 29
13.2.1.2.23
Page 0 / Register 30
13.2.1.2.24
Page 0 / Register 32
13.2.1.2.25
Page 0 / Register 33
13.2.1.2.26
Page 0 / Register 34
13.2.1.2.27
Page 0 / Register 35
13.2.1.2.28
Page 0 / Register 36
13.2.1.2.29
Page 0 / Register 37
13.2.1.2.30
Page 0 / Register 40
13.2.1.2.31
Page 0 / Register 41
13.2.1.2.32
Page 0 / Register 42
13.2.1.2.33
Page 0 / Register 43
13.2.1.2.34
Page 0 / Register 44
13.2.1.2.35
Page 0 / Register 59
13.2.1.2.36
Page 0 / Register 60
13.2.1.2.37
Page 0 / Register 61
13.2.1.2.38
Page 0 / Register 62
13.2.1.2.39
Page 0 / Register 63
13.2.1.2.40
Page 0 / Register 64
13.2.1.2.41
Page 0 / Register 65
13.2.1.2.42
Page 0 / Register 80
13.2.1.2.43
Page 0 / Register 81
13.2.1.2.44
Page 0 / Register 82
13.2.1.2.45
Page 0 / Register 83
13.2.1.2.46
Page 0 / Register 84
13.2.1.2.47
Page 0 / Register 85
13.2.1.2.48
Page 0 / Register 86
13.2.1.2.49
Page 0 / Register 87
13.2.1.2.50
Page 0 / Register 90
13.2.1.2.51
Page 0 / Register 91
13.2.1.2.52
Page 0 / Register 92
13.2.1.2.53
Page 0 / Register 93
13.2.1.2.54
Page 0 / Register 94
13.2.1.2.55
Page 0 / Register 95
13.2.1.2.56
Page 0 / Register 108
13.2.1.2.57
Page 0 / Register 109
13.2.1.2.58
Page 0 / Register 114
13.2.1.2.59
Page 0 / Register 115
13.2.1.2.60
Page 0 / Register 118
13.2.1.2.61
Page 0 / Register 119
13.2.1.2.62
Page 0 / Register 120
13.2.1.2.63
Page 0 / Register 121
13.2.1.2.64
Page 0 / Register 122
13.2.1.2.65
Page 0 / Register 123
13.2.1.2.66
Page 0 / Register 124
13.2.1.2.67
Page 0 / Register 125
11.2
Layout Example
12
Programming
12.1
Coefficient Data Formats
12.2
Power Down and Reset Behavior
13
Register Maps
13.1
PCM5252 Register Map
13.1.1
Detailed Register Descriptions
13.1.1.1
Register Map Summary
13.1.1.2
Page 0 Registers
13.1.1.3
Page 1 Registers
13.1.1.4
Page 44 Registers
13.1.1.5
Page 253 Registers
13.1.2
PLL Tables for Software Controlled Devices
14
Device and Documentation Support
14.1
Community Resources
14.2
Trademarks
14.3
Electrostatic Discharge Caution
15
Mechanical, Packaging, and Orderable Information
14
Device and Documentation Support
14.1
Community Resources
14.2
Trademarks
14.3
Electrostatic Discharge Caution
15
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHB|32
MPQF130D
サーマルパッド・メカニカル・データ
RHB|32
QFND029X
発注情報
slase63_oa
4
Revision History
DATE
REVISION
NOTES
November 2014
*
Initial release.