JAJSNF3A April   2022  – August 2022 PCM6120-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4.     Thermal Information
    5. 7.4  Electrical Characteristics
    6. 7.5  Timing Requirements: I2C Interface
    7. 7.6  Switching Characteristics: I2C Interface
    8. 7.7  Timing Requirements: TDM, I2S or LJ Interface
    9. 7.8  Switching Characteristics: TDM, I2S or LJ Interface
    10.     Timing Requirements: PDM Digital Microphone Interface
    11. 7.9  Switching Characteristics: PDM Digial Microphone Interface
    12. 7.10 Timing Diagrams
    13. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3  Input Channel Configurations
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Programmable Microphone Bias
      6. 8.3.6  Signal-Chain Processing
        1. 8.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.6.2 Programmable Channel Gain Calibration
        3. 8.3.6.3 Programmable Channel Phase Calibration
        4. 8.3.6.4 Programmable Digital High-Pass Filter
        5. 8.3.6.5 Programmable Digital Biquad Filters
        6. 8.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.6.7 Configurable Digital Decimation Filters
          1. 8.3.6.7.1 Linear Phase Filters
            1. 8.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 8.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 8.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 8.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 8.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 8.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 8.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 8.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 8.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 8.3.6.7.2 Low-Latency Filters
            1. 8.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 8.3.6.7.3 Ultra-Low Latency Filters
            1. 8.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 8.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 8.3.7  Dynamic Range Enhancer (DRE)
      8. 8.3.8  Dynamic Range Compressor (DRC)
      9. 8.3.9  Automatic Gain Controller (AGC)
      10. 8.3.10 Voice Activity Detection (VAD)
      11. 8.3.11 Digital PDM Microphone Record Channel
      12. 8.3.12 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode or Software Shutdown
      2. 8.4.2 Active Mode
      3. 8.4.3 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
            1. 8.5.1.1.1.1 I2C Single-Byte and Multiple-Byte Transfers
              1. 8.5.1.1.1.1.1 I2C Single-Byte Write
              2. 8.5.1.1.1.1.2 I2C Multiple-Byte Write
              3. 8.5.1.1.1.1.3 I2C Single-Byte Read
              4. 8.5.1.1.1.1.4 I2C Multiple-Byte Read
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 PCM6120-Q1 Access Codes
      2. 8.6.2 Page 0 Registers
      3. 8.6.3 Page 1 Registers
      4. 8.6.4 Programmable Coefficient Registers
        1. 8.6.4.1 Programmable Coefficient Registers: Page 2
        2. 8.6.4.2 Programmable Coefficient Registers: Page 3
        3. 8.6.4.3 Programmable Coefficient Registers: Page 4
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Two-Channel Analog Microphone Recording
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Four-Channel Digital PDM Microphone Recording
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Example Device Register Configuration Script for EVM Setup
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, and PLL on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC CONFIGURATION
AC input impedance Input pins INxP or INxM, 2.5-kΩ input impedance selection 2.5 kΩ
Input pins INxP or INxM, 10-kΩ input impedance selection 10
Input pins INxP or INxM, 20-kΩ input impednace selection 20
Channel gain range Programmable range with 0.5-dB steps 0 42 dB
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
Differential input full-scale AC signal voltage AC-coupled input 2 VRMS
Single-ended input full-scale AC signal voltage AC-coupled input 1 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection 115 122 dB
IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection 117
IN1 differential input selected and AC signal shorted to ground, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain 106 112
IN1 differential input selected and AC signal shorted to ground, DRE disabled, 2.5-kΩ input impedance selection, 12-dB channel gain 108
DR Dynamic range, A-weighted(2) IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection 123 dB
IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection 118
IN1 differential input selected and –60-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain 113
IN1 differential input selected and –72-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 12-dB channel gain 108
THD+N Total harmonic distortion(2)(3) IN1 differential input selected and –1-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection –95 –80 dB
IN1 differential input selected and –1-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection –95
IN1 differential input selected and –1-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain –95
IN1 differential input selected and –13-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 12-dB channel gain –93
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 1.8-V OPERATION
Differential input full-scale AC signal voltage AC-coupled Input 1 VRMS
Single-ended input full-scale AC signal voltage AC-coupled Input 0.5 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection 116 dB
IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection 111
IN1 differential input selected and AC signal shorted to ground, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain 105
DR Dynamic range, A-weighted(2) IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection 117 dB
IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection 112
IN1 differential input selected and –60-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain 106
THD+N Total harmonic distortion(2)(3) IN1 differential input selected and –2-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection –90 dB
IN1 differential input selected and –2-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection –90
IN1 differential input selected and –2-dB full-scale AC signal Input, DRE disabled, 2.5-kΩ input impedance selection, 0 dB channel gain –90
ADC OTHER PARAMETERS
Digital volume control range Programmable 0.5-dB steps –100 27 dB
Output data sample rate Programmable 7.35 768 kHz
Output data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3-dB point (default setting)		 12 Hz
Interchannel isolation –1-dB full-scale AC-signal input to non measurement channel –124 dB
Interchannel gain mismatch –6-dB full-scale AC-signal input and 0-dB channel gain 0.1 dB
Gain drift(4) 0-dB channel gain, across temperature range –40°C to 125°C 36.8 ppm/°C
Interchannel phase mismatch 1-kHz sinusoidal signal 0.02 Degrees
Phase drift(5) 1-kHz sinusoidal signal, across temperature range –40°C to 125°C 0.0005 Degrees/°C
PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 102 dB
CMRR Common-mode rejection ratio Differential microphone input selected, 0-dB channel gain, 100-mVPP, 1-kHz signal on both pins and measure level at output in high CMRR Mode 80 dB
MICROPHONE BIAS
MICBIAS noise BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AVSS 2.1 µVRMS
MICBIAS voltage MICBIAS programmed to VREF and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V VREF V
MICBIAS programmed to VREF × 1.096 and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V VREF × 1.096
Bypass to AVDD with 5-mA load AVDD – 0.2
MICBIAS current drive 5 mA
MICBIAS load regulation MICBIAS programmed to either VREF or VREF × 1.096, measured up to max load 0 0.6 1 %
MICBIAS over current protection threshold 6.1 mA
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins except IN2P_GPI1 and MICBIAS_GPI2, SDA and SCL, IOVDD 1.8-V operation –0.3 0.35 × IOVDD V
All digital pins except IN2P_GPI1 and MICBIAS_GPI2, SDA and SCL, IOVDD 3.3-V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except IN2P_GPI1 and MICBIAS_GPI2, SDA and SCL, IOVDD 1.8-V operation 0.65 × IOVDD IOVDD + 0.3 V
All digital pins except IN2P_GPI1 and MICBIAS_GPI2, SDA and SCL, IOVDD 3.3-V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except IN2M_GPO1, SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V
All digital pins except IN2M_GPO1, SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation 0.4
VOH High-level digital output voltage All digital pins except IN2M_GPO1, SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V
All digital pins except IN2M_GPO1, SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation 2.4
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 x IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 x IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3 mA, IOVDD > 2 V 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus 20
IIH Input logic-high leakage for digital inputs All digital pins except IN2P_GPI1 and MICBIAS_GPI2 pins, input = IOVDD –5 0.1 5 µA
IIL Input logic-low leakage for digital inputs All digital pins except IN2P_GPI1 and MICBIAS_GPI2 pins, input = 0 V –5 0.1 5 µA
VIL(GPIx) Low-level digital input logic voltage threshold IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 1.8-V operation –0.3 0.35 × AVDD V
IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 3.3-V operation –0.3 0.8
VIH(GPIx) High-level digital input logic voltage threshold IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 1.8-V operation 0.65 × AVDD AVDD + 0.3 V
IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 3.3-V operation 2 AVDD + 0.3
VOL(GPOx) Low-level digital output voltage IN2M_GPO2 digital pin, IOL = –2 mA, AVDD 1.8-V operation 0.45 V
IN2M_GPO2 digital pin, IOL = –2 mA, AVDD 3.3-V operation 0.4
VOH(GPOx) High-level digital output voltage IN2M_GPO2 digital pin, IOH = 2 mA, AVDD 1.8-V operation AVDD – 0.45 V
IN2M_GPO2 digital pin, IOH = 2 mA, AVDD 3.3-V operation 2.4
IIH(GPIx) Input logic-high leakage for digital inputs IN2P_GPI1 and MICBIAS_GPI2 digital pins, input = AVDD –5 0.1 5 µA
IIL(GPIx) Input logic-high leakage for digital inputs IN2P_GPI1 and MICBIAS_GPI2 digital pins, input = 0 V –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode (software shutdown mode) All external clocks stopped, AVDD = 3.3 V, internal AREG 5 µA
IAVDD All external clocks stopped, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 29
IIOVDD All external clocks stopped, IOVDD = 3.3 V 0.5
IIOVDD All external clocks stopped, IOVDD = 1.8 V 0.5
IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, PLL off, BCLK = 512 × fS and DRE disable AVDD = 3.3 V, internal AREG 11.3 mA
IAVDD AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 10.6
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
IAVDD Current consumption with ADC 2-channel operating at fS 16-kHz, PLL on, BCLK = 256 × fS and DRE disable AVDD = 3.3 V, internal AREG 11.5 mA
IAVDD AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 10.8
IIOVDD IOVDD = 3.3 V 0.05
IIOVDD IOVDD = 1.8 V 0.02
IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, PLL on, BCLK = 256 × fS and DRE disable AVDD = 3.3 V, internal AREG 12.4 mA
IAVDD AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 11.7
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, PLL on, BCLK = 256 × fS and DRE enable  AVDD = 3.3 V, internal AREG 13.8 mA
IAVDD AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 13.1
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) For best distortion performance, use input AC-coupling capacitors with low-voltage coefficient.
(4) Gain drift = gain variation (in temperature range) / typical gain value (gain at room temperature) / temperature range × 106 measured with gain in linear scale.
(5) Phase drift = phase deviation (in temperature range) / (temperature range).