JAJSSO6 December   2023 PCM6140-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 6.14 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3  Input Channel Configurations
        1. 7.3.3.1 Common Mode Tolerance Selection
      4. 7.3.4  Reference Voltage
      5. 7.3.5  Programmable Microphone Bias
      6. 7.3.6  Signal-Chain Processing
        1. 7.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 7.3.6.2 Programmable Channel Gain Calibration
        3. 7.3.6.3 Programmable Channel Phase Calibration
        4. 7.3.6.4 Programmable Digital High-Pass Filter
        5. 7.3.6.5 Programmable Digital Biquad Filters
        6. 7.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 7.3.6.7 Configurable Digital Decimation Filters
          1. 7.3.6.7.1 Linear Phase Filters
            1. 7.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 7.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 7.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 7.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 7.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 7.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 7.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 7.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 7.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
          2. 7.3.6.7.2 Low-Latency Filters
            1. 7.3.6.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.6.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.6.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.6.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.6.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 7.3.6.7.2.6 Sampling Rate 192 kHz or 176.4 kHz
          3. 7.3.6.7.3 Ultra-Low-Latency Filters
            1. 7.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 7.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
            7. 7.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
      7. 7.3.7  Dynamic Range Enhancer (DRE)
      8. 7.3.8  Automatic Gain Controller (AGC)
      9. 7.3.9  Digital PDM Microphone Record Channel
      10. 7.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Shutdown
      2. 7.4.2 Sleep Mode or Software Shutdown
      3. 7.4.3 Active Mode
      4. 7.4.4 Software Reset
    5. 7.5 Programming
      1. 7.5.1 Control Serial Interfaces
        1. 7.5.1.1 I2C Control Interface
          1. 7.5.1.1.1 General I2C Operation
          2. 7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 7.5.1.1.2.1 I2C Single-Byte Write
            2. 7.5.1.1.2.2 I2C Multiple-Byte Write
            3. 7.5.1.1.2.3 I2C Single-Byte Read
            4. 7.5.1.1.2.4 I2C Multiple-Byte Read
        2. 7.5.1.2 SPI Control Interface
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration Registers
        1. 7.6.1.1 Register Descriptions
          1. 7.6.1.1.1  PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
          2. 7.6.1.1.2  SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
          3. 7.6.1.1.3  SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
          4. 7.6.1.1.4  SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
          5. 7.6.1.1.5  ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
          6. 7.6.1.1.6  ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
          7. 7.6.1.1.7  ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
          8. 7.6.1.1.8  ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
          9. 7.6.1.1.9  ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
          10. 7.6.1.1.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
          11. 7.6.1.1.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
          12. 7.6.1.1.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
          13. 7.6.1.1.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
          14. 7.6.1.1.14 ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
          15. 7.6.1.1.15 ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
          16. 7.6.1.1.16 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
          17. 7.6.1.1.17 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
          18. 7.6.1.1.18 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
          19. 7.6.1.1.19 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
          20. 7.6.1.1.20 PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
          21. 7.6.1.1.21 PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
          22. 7.6.1.1.22 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
          23. 7.6.1.1.23 GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
          24. 7.6.1.1.24 GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
          25. 7.6.1.1.25 GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
          26. 7.6.1.1.26 GPO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
          27. 7.6.1.1.27 GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
          28. 7.6.1.1.28 GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
          29. 7.6.1.1.29 GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
          30. 7.6.1.1.30 GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
          31. 7.6.1.1.31 GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
          32. 7.6.1.1.32 INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
          33. 7.6.1.1.33 INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
          34. 7.6.1.1.34 INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
          35. 7.6.1.1.35 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
          36. 7.6.1.1.36 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
          37. 7.6.1.1.37 CH1_CFG1 Register (page = 0x00, address = 0x3D) [reset = 0h]
          38. 7.6.1.1.38 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
          39. 7.6.1.1.39 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
          40. 7.6.1.1.40 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
          41. 7.6.1.1.41 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
          42. 7.6.1.1.42 CH2_CFG1 Register (page = 0x00, address = 0x42) [reset = 0h]
          43. 7.6.1.1.43 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
          44. 7.6.1.1.44 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
          45. 7.6.1.1.45 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
          46. 7.6.1.1.46 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
          47. 7.6.1.1.47 CH3_CFG1 Register (page = 0x00, address = 0x47) [reset = 0h]
          48. 7.6.1.1.48 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
          49. 7.6.1.1.49 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
          50. 7.6.1.1.50 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
          51. 7.6.1.1.51 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
          52. 7.6.1.1.52 CH4_CFG1 Register (page = 0x00, address = 0x4C) [reset = 0h]
          53. 7.6.1.1.53 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
          54. 7.6.1.1.54 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
          55. 7.6.1.1.55 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
          56. 7.6.1.1.56 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
          57. 7.6.1.1.57 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
          58. 7.6.1.1.58 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
          59. 7.6.1.1.59 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
          60. 7.6.1.1.60 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
          61. 7.6.1.1.61 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
          62. 7.6.1.1.62 CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
          63. 7.6.1.1.63 CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
          64. 7.6.1.1.64 CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
          65. 7.6.1.1.65 CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
          66. 7.6.1.1.66 CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
          67. 7.6.1.1.67 CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
          68. 7.6.1.1.68 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
          69. 7.6.1.1.69 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
          70. 7.6.1.1.70 DRE_CFG0 Register (page = 0x00, address = 0x6D) [reset = 7Bh]
          71. 7.6.1.1.71 AGC_CFG0 Register (page = 0x00, address = 0x70) [reset = E7h]
          72. 7.6.1.1.72 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
          73. 7.6.1.1.73 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
          74. 7.6.1.1.74 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
          75. 7.6.1.1.75 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
          76. 7.6.1.1.76 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
          77. 7.6.1.1.77 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
      2. 7.6.2 Programmable Coefficient Registers
        1. 7.6.2.1 Programmable Coefficient Registers: Page = 0x02
        2. 7.6.2.2 Programmable Coefficient Registers: Page = 0x03
        3. 7.6.2.3 Programmable Coefficient Registers: Page = 0x04
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Four-Channel Analog Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Eight-Channel Digital PDM Microphone Recording
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Example Device Register Configuration Script for EVM Setup
    3. 8.3 What to Do and What Not to Do
      1. 8.3.1 187
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ADC CONFIGURATION
AC input impedanceInput pins INxP or INxM, 2.5-kΩ input impedance selection2.5kΩ
Input pins INxP or INxM, 10-kΩ input impedance selection10
Input pins INxP or INxM, 20-kΩ input impednace selection20
Channel gain rangeProgrammable range with 1-dB steps042dB
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
Differential input full-scale AC signal voltageAC-coupled input2VRMS
Single-ended input full-scale AC signal voltageAC-coupled input1VRMS
SNRSignal-to-noise ratio, A-weighted(1)(2)IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection115122dB
IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection117
IN1 differential input selected and AC signal shorted to ground, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain106112
IN1 differential input selected and AC signal shorted to ground, DRE disabled, 2.5-kΩ input impedance selection, 12-dB channel gain108
DRDynamic range, A-weighted(2)IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection123dB
IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection118
IN1 differential input selected and –60-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain113
IN1 differential input selected and –72-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 12-dB channel gain108
THD+NTotal harmonic distortion(2)(3)IN1 differential input selected and –1-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection–98–80dB
IN1 differential input selected and –1-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection–98
IN1 differential input selected and –1-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain–98
IN1 differential input selected and –13-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 12-dB channel gain–98
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 1.8-V OPERATION
Differential input full-scale AC signal voltageAC-coupled Input1VRMS
Single-ended input full-scale AC signal voltageAC-coupled Input0.5VRMS
SNRSignal-to-noise ratio, A-weighted(1)(2)IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection116dB
IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection111
IN1 differential input selected and AC signal shorted to ground, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain105
DRDynamic range, A-weighted(2)IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection117dB
IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection112
IN1 differential input selected and –60-dB full-scale AC signal input, DRE disabled, 2.5-kΩ input impedance selection, 0-dB channel gain106
THD+NTotal harmonic distortion(2)(3)IN1 differential input selected and –2-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 2.5-kΩ input impedance selection–90dB
IN1 differential input selected and –2-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB), 10-kΩ input impedance selection–90
IN1 differential input selected and –2-dB full-scale AC signal Input, DRE disabled, 2.5-kΩ input impedance selection, 0 dB channel gain–90
ADC OTHER PARAMETERS
Digital volume control rangeProgrammable 0.5-dB steps–10027dB
Output data sample rateProgrammable7.35768kHz
Output data sample word lengthProgrammable1632Bits
Digital high-pass filter cutoff frequencyFirst-order IIR filter with programmable coefficients, –3-dB point (default setting)12Hz
Interchannel isolation–1-dB full-scale AC-signal input to non measurement channel–124dB
Interchannel gain mismatch–6-dB full-scale AC-signal input and 0-dB channel gain0.1dB
Gain drift0-dB channel gain, across temperature range 15°C to 35°C–4.4ppm/°C
Interchannel phase mismatch1-kHz sinusoidal signal0.02Degrees
Phase drift1-kHz sinusoidal signal, across temperature range 15°C to 35°C0.0005Degrees/°C
PSRRPower-supply rejection ratio100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain102dB
CMRRCommon-mode rejection ratioDifferential microphone input selected, 0-dB channel gain, 100-mVPP, 1-kHz signal on both pins and measure level at output60dB
MICROPHONE BIAS
MICBIAS noiseBW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AVSS1.6µVRMS
MICBIAS voltageMICBIAS programmed to VREF and VREF programmed to either 2.75 V, 2.5 V, or 1.375 VVREFV
MICBIAS programmed to VREF × 1.096 and VREF programmed to either 2.75 V, 2.5 V, or 1.375 VVREF × 1.096
Bypass to AVDD with 20-mA loadAVDD – 0.2
MICBIAS current driveMICBIAS voltage ≥ 2.5 V20mA
MICBIAS voltage < 2.5 V10
MICBIAS load regulationMICBIAS programmed to either VREF or VREF × 1.096, measured up to max load00.61.8%
MICBIAS over current protection threshold30mA
DIGITAL I/O
VIL(SHDNZ)Low-level digital input logic voltage thresholdSHDNZ pin–0.30.25 × IOVDDV
VIH(SHDNZ)High-level digital input logic voltage thresholdSHDNZ pin0.75 × IOVDDIOVDD + 0.3V
VILLow-level digital input logic voltage thresholdAll digital pins except INxP_GPIx, SDA and SCL, IOVDD 1.8-V operation–0.30.35 × IOVDDV
All digital pins except INxP_GPIx, SDA and SCL, IOVDD 3.3-V operation–0.30.8
VIHHigh-level digital input logic voltage thresholdAll digital pins except INxP_GPIx, SDA and SCL, IOVDD 1.8-V operation0.65 × IOVDDIOVDD + 0.3V
All digital pins except INxP_GPIx, SDA and SCL, IOVDD 3.3-V operation2IOVDD + 0.3
VOLLow-level digital output voltageAll digital pins except INxM_GPOx, SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation0.45V
All digital pins except INxM_GPOx, SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation0.4
VOHHigh-level digital output voltageAll digital pins except INxM_GPOx, SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operationIOVDD – 0.45V
All digital pins except INxM_GPOx, SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation2.4
VIL(I2C)Low-level digital input logic voltage thresholdSDA and SCL–0.50.3 x IOVDDV
VIH(I2C)High-level digital input logic voltage thresholdSDA and SCL0.7 x IOVDDIOVDD + 0.5V
VOL1(I2C)Low-level digital output voltageSDA, IOL(I2C) = –3 mA, IOVDD > 2 V0.4V
VOL2(I2C)Low-level digital output voltageSDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V0.2 x IOVDDV
IOL(I2C)Low-level digital output currentSDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode3mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus20
IIHInput logic-high leakage for digital inputsAll digital pins except INxP_GPIx pins, input = IOVDD–50.15µA
IILInput logic-low leakage for digital inputsAll digital pins except INxP_GPIx pins, input = 0 V–50.15µA
VIL(GPIx)Low-level digital input logic voltage thresholdAll INxP_GPIx digital pins, AVDD 1.8-V operation–0.30.35 × AVDDV
All INxP_GPIx digital pins, AVDD 3.3-V operation–0.30.8
VIH(GPIx)High-level digital input logic voltage thresholdAll INxP_GPIx digital pins, AVDD 1.8-V operation0.65 × AVDDAVDD + 0.3V
All INxP_GPIx digital pins, AVDD 3.3-V operation2AVDD + 0.3
VOL(GPOx)Low-level digital output voltageAll INxM_GPOx digital pins, IOL = –2 mA, AVDD 1.8-V operation0.45V
All INxM_GPOx digital pins, IOL = –2 mA, AVDD 3.3-V operation0.4
VOH(GPOx)High-level digital output voltageAll INxM_GPOx digital pins, IOH = 2 mA, AVDD 1.8-V operationAVDD – 0.45V
All INxM_GPOx digital pins, IOH = 2 mA, AVDD 3.3-V operation2.4
IIH(GPIx)Input logic-high leakage for digital inputsAll INxP_GPIx digital pins, input = AVDD–50.15µA
IIL(GPIx)Input logic-high leakage for digital inputsAll INxP_GPIx digital pins, input = 0 V–50.15µA
CINInput capacitance for digital inputsAll digital pins5pF
RPDPulldown resistance for digital I/O pins when asserted on20kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDDCurrent consumption in hardware shutdown modeSHDNZ = 0, AVDD = 3.3 V, internal AREG0.5µA
IAVDDSHDNZ = 0, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)0.5
IIOVDDSHDNZ = 0, all external clocks stopped, IOVDD = 3.3 V0.1
IIOVDDSHDNZ = 0, all external clocks stopped, IOVDD = 1.8 V0.1
IAVDDCurrent consumption in sleep mode (software shutdown mode)All external clocks stopped, AVDD = 3.3 V, internal AREG5µA
IAVDDAll external clocks stopped, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)5
IIOVDDAll external clocks stopped, IOVDD = 3.3 V0.1
IIOVDDAll external clocks stopped, IOVDD = 1.8 V0.1
IAVDDCurrent consumption with ADC 2-channel operating at fS 48-kHz, PLL off, BCLK = 512 × fS and DRE disableAVDD = 3.3 V, internal AREG11.3mA
IAVDDAVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)10.7
IIOVDDIOVDD = 3.3 V0.1
IIOVDDIOVDD = 1.8 V0.05
IAVDDCurrent consumption with ADC 4-channel operating at fS 16-kHz, PLL on, BCLK = 256 × fS and DRE disableAVDD = 3.3 V, internal AREG19.7mA
IAVDDAVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)18.6
IIOVDDIOVDD = 3.3 V0.05
IIOVDDIOVDD = 1.8 V0.02
IAVDDCurrent consumption with ADC 4-channel operating at fS 48-kHz, PLL on, BCLK = 256 × fS and DRE disableAVDD = 3.3 V, internal AREG21.3mA
IAVDDAVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)20.2
IIOVDDIOVDD = 3.3 V0.1
IIOVDDIOVDD = 1.8 V0.05
IAVDDCurrent consumption with ADC 4-channel operating at fS 48-kHz, PLL on, BCLK = 256 × fS and DRE enable AVDD = 3.3 V, internal AREG23.6mA
IAVDDAVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)22.3
IIOVDDIOVDD = 3.3 V0.1
IIOVDDIOVDD = 1.8 V0.05
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) For best distortion performance, use input AC-coupling capacitors with low-voltage-coefficient.