JAJSSO6 December 2023 PCM6140-Q1
ADVANCE INFORMATION
In controller mode operation with I2S or LJ format, the device generates FSYNC half a cycle earlier than the normal protocol timing behavior expected. This timing behavior can still function for most of the system, however for further details and a suggested workaround for this weakness, see the Configuring and Operating the TLV320ADCx140 as an Audio Bus Master application report.
The automatic gain controller (AGC) feature has some limitation when using sampling rates lower than 44.1 kHz. For further details about this limitation, see the Using the Automatic Gain Controller (AGC) in TLV320ADCx140 application report.