JAJSSH9A May 2023 – January 2024 PCMD3180-Q1
PRODUCTION DATA
This register is the latched Interrupt readback register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LTCH0[7] | INT_LTCH0[6] | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LTCH0[7] | R | 0h | Interrupt caused by an ASI bus clock error (self-clearing bit). 0d = No interrupt 1d = Interrupt |
6 | INT_LTCH0[6] | R | 0h | Interrupt caused by PLL LOCK (self-clearing bit). 0d = No interrupt 1d = Interrupt |
5-0 | Reserved | R | 0h | Reserved |