JAJSSH9A May 2023 – January 2024 PCMD3180-Q1
PRODUCTION DATA
This register configures the device shutdown
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Reserved | SHDNZ_CFG[1:0] | DREG_KA_TIME[1:0] | ||||
R-0h | R/W-0h | R/W-1h | R/W-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | Reserved | R | 0h | Reserved |
5-4 | Reserved | R/W | 0h | Reserved |
3-2 | SHDNZ_CFG[1:0] | R/W | 1h | Shutdown configuration. 0d = DREG is powered down immediately after SHDNZ asserts 1d = DREG remains active to enable a clean shut down until a time-out is reached; after the time-out period, DREG is forced to power off 2d = DREG remains active until the device cleanly shuts down 3d = Reserved |
1-0 | DREG_KA_TIME[1:0] | R/W | 1h | These bits set how long DREG remains active after SHDNZ asserts. 0d = DREG remains active for 30 ms (typical) 1d = DREG remains active for 25 ms (typical) 2d = DREG remains active for 10 ms (typical) 3d = DREG remains active for 5 ms (typical) |