JAJSSH9A May 2023 – January 2024 PCMD3180-Q1
PRODUCTION DATA
This register is configuration register 0 for Channel 5.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | CH5_INSRC[1:0] | Reserved | |||||
R-0h | R/W-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | R | 0h | Reserved |
6-5 | CH5_INSRC[1:0] | R/W | 0h | Channel 5 Input Configuration 0d = Digital microphone PDM input (configure the GPO and GPI pins accordingly for PDMDIN3 and PDMCLK) 1d = Digital microphone PDM input (configure the GPO and GPI pins accordingly for PDMDIN3 and PDMCLK) 2d = Digital microphone PDM input (configure the GPO and GPI pins accordingly for PDMDIN3 and PDMCLK) 3d = Reserved |
4-0 | Reserved | R | 0h | Reserved |