JAJSSH9A May   2023  – January 2024 PCMD3180-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Reference Voltage
      4. 6.3.4 Microphone Bias
      5. 6.3.5 Digital PDM Microphone Record Channel
      6. 6.3.6 Signal-Chain Processing
        1. 6.3.6.1 Programmable Digital Volume Control
        2. 6.3.6.2 Programmable Channel Gain Calibration
        3. 6.3.6.3 Programmable Channel Phase Calibration
        4. 6.3.6.4 Programmable Digital High-Pass Filter
        5. 6.3.6.5 Programmable Digital Biquad Filters
        6. 6.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 6.3.6.7 Configurable Digital Decimation Filters
          1. 6.3.6.7.1 Linear Phase Filters
            1. 6.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 6.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 6.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 6.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 6.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 6.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 6.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 6.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 6.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
          2. 6.3.6.7.2 Low-Latency Filters
            1. 6.3.6.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 6.3.6.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 6.3.6.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 6.3.6.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 6.3.6.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 6.3.6.7.2.6 Sampling Rate 192 kHz or 176.4 kHz
          3. 6.3.6.7.3 Ultra-Low-Latency Filters
            1. 6.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 6.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 6.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 6.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 6.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 6.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
            7. 6.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
      7. 6.3.7 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Shutdown
      2. 6.4.2 Sleep Mode or Software Shutdown
      3. 6.4.3 Active Mode
      4. 6.4.4 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 Register Summary Table Page=0x00
      2. 7.1.2 88
      3. 7.1.3 Register Descriptions
        1. 7.1.3.1  PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
        2. 7.1.3.2  SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
        3. 7.1.3.3  SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
        4. 7.1.3.4  SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
        5. 7.1.3.5  ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
        6. 7.1.3.6  ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
        7. 7.1.3.7  ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
        8. 7.1.3.8  ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
        9. 7.1.3.9  ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
        10. 7.1.3.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
        11. 7.1.3.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
        12. 7.1.3.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
        13. 7.1.3.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
        14. 7.1.3.14 ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
        15. 7.1.3.15 ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
        16. 7.1.3.16 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
        17. 7.1.3.17 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
        18. 7.1.3.18 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
        19. 7.1.3.19 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
        20. 7.1.3.20 PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
        21. 7.1.3.21 PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
        22. 7.1.3.22 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
        23. 7.1.3.23 GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
        24. 7.1.3.24 GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
        25. 7.1.3.25 GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
        26. 7.1.3.26 PO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
        27. 7.1.3.27 GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
        28. 7.1.3.28 GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
        29. 7.1.3.29 GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
        30. 7.1.3.30 GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
        31. 7.1.3.31 GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
        32. 7.1.3.32 INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
        33. 7.1.3.33 INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
        34. 7.1.3.34 INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
        35. 7.1.3.35 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
        36. 7.1.3.36 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
        37. 7.1.3.37 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
        38. 7.1.3.38 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
        39. 7.1.3.39 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
        40. 7.1.3.40 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
        41. 7.1.3.41 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
        42. 7.1.3.42 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
        43. 7.1.3.43 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
        44. 7.1.3.44 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
        45. 7.1.3.45 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
        46. 7.1.3.46 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
        47. 7.1.3.47 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
        48. 7.1.3.48 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
        49. 7.1.3.49 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
        50. 7.1.3.50 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
        51. 7.1.3.51 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
        52. 7.1.3.52 CH5_CFG0 Register (page = 0x00, address = 0x50) [reset = 0h]
        53. 7.1.3.53 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
        54. 7.1.3.54 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
        55. 7.1.3.55 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
        56. 7.1.3.56 CH6_CFG0 Register (page = 0x00, address = 0x55) [reset = 0h]
        57. 7.1.3.57 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
        58. 7.1.3.58 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
        59. 7.1.3.59 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
        60. 7.1.3.60 CH7_CFG0 Register (page = 0x00, address = 0x5A) [reset = 0h]
        61. 7.1.3.61 CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
        62. 7.1.3.62 CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
        63. 7.1.3.63 CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
        64. 7.1.3.64 CH8_CFG0 Register (page = 0x00, address = 0x5F) [reset = 0h]
        65. 7.1.3.65 CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
        66. 7.1.3.66 CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
        67. 7.1.3.67 CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
        68. 7.1.3.68 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
        69. 7.1.3.69 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
        70. 7.1.3.70 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
        71. 7.1.3.71 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
        72. 7.1.3.72 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
        73. 7.1.3.73 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
        74. 7.1.3.74 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
        75. 7.1.3.75 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1 Programmable Coefficient Registers: Page = 0x02
      2. 7.2.2 Programmable Coefficient Registers: Page = 0x03
      3. 7.2.3 Programmable Coefficient Registers: Page = 0x04
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Eight-Channel Digital PDM Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 8.2.1.3 Application Curves
    3. 8.3 What to Do and What Not to Do
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.1.3 Using Multiple Devices With Shared Buses

The device has many supported features and flexible options that can be used in the system to seamlessly connect multiple PCMD3180-Q1 devices by sharing a single common I2C control bus and an audio serial interface bus. This architecture enables multiple applications to be applied to a system that require a microphone array for beam-forming operation, audio conferencing, noise cancellation, and so forth. Figure 6-13 shows a diagram of multiple PCMD3180-Q1 devices in a configuration where the control and audio data buses are shared.

GUID-99CFB8AD-F801-46AE-B67F-42EDEC34F04A-low.gifFigure 6-13 Multiple PCMD3180-Q1 Devices With Shared Control and Audio Data Buses

The PCMD3180-Q1 consists of the following features to enable seamless connection and interaction of multiple devices using a shared bus:

  • Supports up to four pin-programmable I2C slave addresses
  • I2C broadcast simultaneously writes to (or triggers) all PCMD3180-Q1 devices
  • Supports up to 64 configuration output channel slots for the audio serial interface
  • Tri-state feature (with enable and disable) for the unused audio data slots of the device
  • Supports a bus-holder feature (with enable and disable) to keep the last driven value on the audio bus
  • The GPIO1 or GPOx pin can be configured as a secondary output data lane for the audio serial interface
  • The GPIO1 or GPIx pin can be used in a daisy-chain configuration of multiple PCMD3180-Q1 devices
  • Supports one BCLK cycle data latching timing to relax the timing requirement for the high-speed interface
  • Programmable master and slave options for the audio serial interface
  • Ability to synchronize the multiple devices for the simultaneous sampling requirement across devices
The system can also connect multiple PCMD3180-Q1 devices in combination with TLV320ADCx140 devices by sharing a single common I2C control bus and an audio serial interface bus. See the Multiple TLV320ADCx140 Devices With Shared TDM and I2C Bus application report for further details.