JAJSSH9A May 2023 – January 2024 PCMD3180-Q1
PRODUCTION DATA
This register is the PDM clock generation configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Reserved | PDMCLK_DIV[1:0] | |||||
R/W-0h | R/W-10h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | R/W | 0h | Reserved |
6-2 | Reserved | R/W | 10h | Reserved |
1-0 | PDMCLK_DIV[1:0] | R/W | 0h | PDMCLK divider value. 0d = PDMCLK is 2.8224 MHz or 3.072 MHz 1d = PDMCLK is 1.4112 MHz or 1.536 MHz 2d = PDMCLK is 705.6 kHz or 768 kHz 3d = PDMCLK is 5.6448 MHz or 6.144 MHz |