JAJSQY9 august   2023 REF35-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Solder Heat Shift
    2. 8.2 Temperature Coefficient
    3. 8.3 Long-Term Stability
    4. 8.4 Thermal Hysteresis
    5. 8.5 Noise Performance
      1. 8.5.1 Low-Frequency (1/f) Noise
      2. 8.5.2 Broadband Noise
    6. 8.6 Power Dissipation
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply Voltage
      2. 9.3.2 EN Pin
      3. 9.3.3 NR Pin
    4. 9.4 Device Functional Modes
      1. 9.4.1 Basic Connections
      2. 9.4.2 Start-Up
      3. 9.4.3 Output Transient Behavior
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Negative Reference Voltage
    3. 10.3 Typical Application: Precision Power Supply and Reference
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure
        1. 10.3.2.1 Selection of Reference
        2. 10.3.2.2 Input and Output Capacitors
        3. 10.3.2.3 Selection of ADC
      3. 10.3.3 Application Curves
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4.3 Output Transient Behavior

The REF35-Q1 output buffer is capable of sourcing 10 mA load current as well as sink 5 mA of load current. The output stage is designed using class AB architecture with ultra-low quiescent current. This architecture avoids the dead zone around the no load condition. The output buffer uses a fast start-up implementation to achieve 2ms typical turn-on time at CL = 1 μF and no-load current condition.

Figure 9-3 and Figure 9-4 show the output settling behavior for light load transient and high load transient respectively.

GUID-20220811-SS0I-JQ01-CT2T-RFXGVCFCSHBB-low.svgFigure 9-3 Load Transient Response 0 μA to 100 μA, CREF = 1 μF
GUID-20220811-SS0I-WWXM-ZRQ4-QXHRXMKKGJ28-low.svgFigure 9-4 Load Transient Response 1 mA to 10 mA, CREF = 1 μF