JAJSS97 December   2023 RES11A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 DC Measurement Configurations
    2. 6.2 AC Measurement Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ratiometric Matching
      2. 7.3.2 Ratiometric Drift
      3. 7.3.3 Predictable Voltage Coefficient
      4. 7.3.4 Ultra-Low Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Discrete Difference Amplifier
        1. 8.1.1.1 Difference-Amplifier Common-Mode Rejection Analysis
      2. 8.1.2 Discrete Instrumentation Amplifiers
        1. 8.1.2.1 Instrumentation Amplifier Common-Mode Rejection Analysis
      3. 8.1.3 Fully Differential Amplifier
    2. 8.2 Typical Application
      1. 8.2.1 Common-Mode Shifting Input Stage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
        3. 9.1.1.3 TI のリファレンス・デザイン
        4. 9.1.1.4 フィルタ設計ツール
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DDF|8
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INITIAL RESISTANCE
Gnom Nominal ratio (RGx / RINx) RES11A10 1 V/V
RES11A15 1.5
RES11A16 1.667
RES11A20 2
RES11A25 2.5
RES11A30 3
RES11A40 4
RES11A50 5
RES11A90 9
RES11A00 10
tD1 Ratio tolerance of divider 1 (1) (RG1 / RIN1) / Gnom – 1 RES11A10 ±500 ppm
RES11A15 ±500
RES11A16 ±500
RES11A20 ±500
RES11A25 ±500
RES11A30 ±500
RES11A40 ±120 ±500
RES11A50 ±500
RES11A90 ±500
RES11A00 ±500
Voltage-divider circuit tolerance of divider 1 (1 + Gnom) ×
(RIN1 / (RIN1 + RG1)) – 1		 RES11A10 ±500 ppm
RES11A15 ±500
RES11A16 ±500
RES11A20 ±500
RES11A25 ±500
RES11A30 ±500
RES11A40 ±100 ±500
RES11A50 ±500
RES11A90 ±500
RES11A00 ±500
tD2 Ratio tolerance of divider 2 (1) (RG2 / RIN2) / Gnom – 1 RES11A10 ±500 ppm
RES11A15 ±500
RES11A16 ±500
RES11A20 ±500
RES11A25 ±500
RES11A30 ±500
RES11A40 ±120 ±500
RES11A50 ±500
RES11A90 ±500
RES11A00 ±500
Voltage-divider circuit tolerance of divider 2 (1 + Gnom) ×
(RIN2 / (RIN2 + RG2)) – 1		 RES11A10 ±500 ppm
RES11A15 ±500
RES11A16 ±500
RES11A20 ±500
RES11A25 ±500
RES11A30 ±500
RES11A40 ±100 ±500
RES11A50 ±500
RES11A90 ±500
RES11A00 ±500
tM Matching tolerance of dividers 1 and 2 tD2 – tD1 RES11A10 ±1000 ppm
RES11A15 ±1000
RES11A16 ±1000
RES11A20 ±1000
RES11A25 ±1000
RES11A30 ±1000
RES11A40 ±85 ±1000
RES11A50 ±1000
RES11A90 ±1000
RES11A00 ±1000
tabs Absolute tolerance (per resistor)(2) (Rx / Rxnom) – 1 (3) ±2 ±12 %
Absolute tolerance span MAX (tabsRIN1, tabsRG1, tabsRIN2, tabsRG2) – MIN (tabsRIN1, tabsRG1, tabsRIN2, tabsRG2) ±235 ppm
RESISTANCE DRIFT
Absolute temperature coefficient of resistance (per resistor) (4) (ΔRx / Rx(25°C)) / ΔTA TA = –40C to +125°C ±18 ppm/°C
Divider temperature coefficient of resistance (per divider) (4) ΔtDx / ΔTA TA = –40C to +125°C –0.2 ±2 ppm/°C
TCR Matching temperature coefficient of resistance (4) ΔtM / ΔTA TA = –40C to +125°C ±0.05 ppm/°C
Absolute voltage coefficient of resistance (per resistor)(2) (4) ΔRINx / ΔVRINx VRINx = 0 V to
VRINx = 40 V		 ±0.02 Ω/V
ΔRGx / (ΔVRGx × Gnom) VRGx = 0 V to
VRGx = 40 V		 ±0.02
Divider voltage coefficient of resistance (per divider) (4) ΔtDx / ΔVDx VDx = 0 V to VDx = 40 V ±2 ppm/V
VCR Matching voltage coefficient of resistance (4) (ΔtD2 – ΔtD1) / ΔVDx VDx = 0 V to VDx = 40 V ±0.5 ppm/V
IMPEDANCE
CIN Pin capacitance (4) RINx to GND/SUB 2.2 pF
RGx to GND/SUB 1.6
RMIDx to GND/SUB 3.3
Crosstalk (RMID1 to RMID2) (4) Substrate biased to GND f = 10 kHz –100 dB
f = 1 MHz –64
Substrate floating f = 10 kHz –98
f = 1 MHz –56
–3-dB bandwidth (4) Substrate biased to GND 35 MHz
Substrate floating 40
CMRR Common-mode rejection ratio (5) RES11A10 66.0 dB
RES11A15 68.0
RES11A16 68.5
RES11A20 69.5
RES11A25 70.9
RES11A30 72.0
RES11A40 74.0 95.4
RES11A50 75.6
RES11A90 80.0
RES11A00 80.8
(1) Relation of RG1 / RIN1 or RG2 / RIN2 to nominal ratio.
(2) Relation of RG1, RIN1, RG2, or RIN2 to nominal resistance.
(3) The specification is the result of this expression, given as a percentage (multiplied by 100%).
(4) Specified by characterization.
(5) The specification is the calculated CMRR when implemented in a difference amplifier configuration with an ideal op-amp, such that the only source of common-mode error is the resistor network. See the Optimizing CMRR in Differential Amplifier Circuits With Precision Matched Resistor Divider Pairs application note for more information. Effects over frequency are not included. If the circuit is configured in an attenuating gain, this result changes accordingly.