SLAS740A January 2013 – October 2015 RF430F5978
PRODUCTION DATA.
Figure 4-1 shows the pinout of the 64-pin RGC package.
NOTE:
The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows the default mapping. See Table 6-8 for details.Table 4-1 describes the signals.
TERMINAL | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
P2.0/PM_CBOUT1/PM_TA1CLK/ CB0/A0 | 1 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Comparator_B output Default mapping: Timer1_A3 clock input Comparator input CB0 Analog input A0 – 12-bit ADC |
P1.7/ PM_UCA0CLK/PM_UCB0STE | 2 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_A0 clock input/output Default mapping: USCI_B0 SPI slave transmit enable |
P1.6/ PM_UCA0TXD/PM_UCA0SIMO | 3 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_A0 UART transmit data Default mapping: USCI_A0 SPI slave in/master out |
P1.5/ PM_UCA0RXD/PM_UCA0SOMI | 4 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_A0 UART receive data Default mapping: USCI_A0 SPI slave out/master in |
VCORE | 5 | S | Regulated core power supply |
DVCC | 6 | S | Digital power supply |
P1.4/ PM_UCB0CLK/PM_UCA0STE | 7 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 clock input/output Default mapping: USCI_A0 SPI slave transmit enable |
P1.3/ PM_UCB0SIMO/PM_UCB0SDA | 8 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 SPI slave in/master out Default mapping: USCI_B0 I2C data |
P1.2/ PM_UCB0SOMI/PM_UCB0SCL | 9 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 SPI slave out/master in Default mapping: UCSI_B0 I2C clock |
P1.1/PM_RFGDO2 | 10 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Radio GDO2 output |
P1.0/PM_RFGDO0 | 11 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Radio GDO0 output |
P3.7/PM_SMCLK | 12 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: SMCLK output |
AFE_VCL | 13 | A | Charge capacitor and supply voltage for immobilizer mode |
AFE_RF1 | 14 | A | Connection for resonant circuit 1 |
AFE_RF2 | 15 | A | Connection for resonant circuit 2 |
AFE_RF3 | 16 | A | Connection for resonant circuit 3 |
AFE_GND | 17 | Analog LF front end GND | |
AFE_TEN | 18 | I | Test interface enable of analog LF front end |
AFE_TDAT | 19 | I/O | Test interface data of analog LF front end |
AFE_TCLK | 20 | I | Test interface clock of analog LF front end |
AFE_ACTI | 21 | A | Test interface output of analog front end |
AFE_VCCSW | 22 | A | Switched power supply buffer (external capacitor) |
VBAT | 23 | S | Supply voltage analog front end |
GNDA | 24 | G | Analog ground |
WAKE | 25 | O | Analog ground |
NC | 26 | Not connected | |
SW0 | 27 | I | Switch input with internal pullup resistor |
SW1 | 28 | I | Switch input with internal pullup resistor |
SW2 | 29 | I | Switch input with internal pullup resistor |
SW3 | 30 | I | Switch input with internal pullup resistor |
SW4 | 31 | I | Switch input with internal pullup resistor |
NC | 32 | Not connected | |
P4.0 | 33 | I/O | General-purpose digital I/O |
SW5 | 34 | I | Switch input with internal pullup resistor |
SW6 | 35 | I | Switch input with internal pullup resistor |
SW7 | 36 | I | Switch input with internal pullup resistor |
RF_XIN | 37 | I | Input terminal for RF crystal oscillator or external clock input |
RF_XOUT | 38 | O | Output terminal for RF crystal oscillator |
RF_AVCC | 39 | S | Radio analog power supply |
RF_GND | 40 | G | Radio ground |
RF_AVCC | 41 | S | Radio analog power supply |
RF_GND | 42 | G | Radio ground |
RF_P | 43 | RF I/O | Positive RF input to LNA in receive mode Positive RF output from PA in transmit mode |
RF_N | 44 | RF I/O | Negative RF input to LNA in receive mode Negative RF output from PA in transmit mode |
RF_GND | 45 | G | Radio ground |
RF_AVCC | 46 | S | Radio analog power supply |
RF_RBIAS | 47 | External bias resistor for radio reference current | |
RF_AVCC | 48 | I/O | Radio analog power supply |
PJ.0/TDO | 49 | I/O | General-purpose digital I/O or test data output port |
PJ.1/TDI/TCLK | 50 | I/O | General-purpose digital I/O or test data input or test clock input |
PJ.2/TMS | 51 | I/O | General-purpose digital I/O or test mode select |
PJ.3/TCK | 52 | I/O | General-purpose digital I/O or test clock |
TEST/SBWTCK | 53 | I | Test mode pin – select digital I/O on JTAG pins or Spy-Bi-Wire input clock |
RST/NMI/SBWTDIO | 54 | I/O | Reset input active low Nonmaskable interrupt input Spy-Bi-Wire data input/output |
DVCC | 55 | S | Digital power supply |
DGND | 56 | G | Digital ground supply |
AGND | 57 | G | Analog ground supply |
P5.1/XOUT | 58 | I/O | General-purpose digital I/O Output terminal of crystal oscillator XT1 |
P5.0/XIN | 59 | I/O | General-purpose digital I/O Input terminal for crystal oscillator XT1 |
AVCC | 60 | S | Analog power supply |
P2.5/PM_SVMOUT/CB5/A5/ VREF+/VeREF+ | 61 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: SVM output Comparator input CB5 Analog input A5 – ADC Output of positive reference voltage Input for an external positive reference voltage to the ADC |
P2.4/PM_RTCCLK/CB4/A4/ VREF-/VeREF- | 62 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: RTCCLK output Comparator input CB4 Analog input A4 – ADC Output of negative reference voltage Input for an external negative reference voltage to the ADC |
P2.2/PM_TA1CCR1A/CB2/A2 | 63 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: TA1 CCR1 compare output/capture input Comparator input CB2 Analog input A2 – ADC |
P2.1/PM_TA1CCR0A/CB1/A1 | 64 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: TA1 CCR0 compare output/capture input Comparator input CB1 Analog input A1 – ADC |
Exposed die attach pad | Ground supply The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip. |