SPNS180B September 2012 – June 2015 RM42L432
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
ABBREVIATION | FULL NAME |
---|---|
MibADC | Multibuffered Analog-to-Digital Converter |
CCM-R4 | CPU Compare Module – Cortex-R4 |
CRC | Cyclic Redundancy Check |
DCAN | Controller Area Network |
DCC | Dual Clock Comparator |
ESM | Error Signaling Module |
GIO | General-Purpose Input/Output |
HTU | High-End Timer Transfer Unit |
LIN | Local Interconnect Network |
MibSPI | Multibuffered Serial Peripheral Interface |
N2HET | Platform High-End Timer |
RTI | Real-Time Interrupt Module |
SCI | Serial Communications Interface |
SPI | Serial Peripheral Interface |
VIM | Vectored Interrupt Manager |
eQEP | Enhanced Quadrature Encoder Pulse |
The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO unless otherwise noted.
DESCRIPTION | VALUE |
---|---|
Resolution | 12 bits |
Monotonic | Assured |
Output conversion code | 00h to FFFh [00 for VAI ≤ ADREFLO; FFF for VAI ≥ ADREFHI] |
The ADC module supports three conversion groups: Event Group, Group1, and Group2. Each of these three groups can be configured to be hardware event-triggered. In that case, the application can select from among eight event sources to be the trigger for the conversions of a group.
EVENT NUMBER | SOURCE SELECT BITS For G1, G2, or EVENT (G1SRC[2:0], G2SRC[2:0], or EVSRC[2:0]) |
TRIGGER |
---|---|---|
1 | 000 | ADEVT |
2 | 001 | N2HET[8] |
3 | 010 | N2HET[10] |
4 | 011 | RTI compare 0 interrupt |
5 | 100 | N2HET[12] |
6 | 101 | N2HET[14] |
7 | 110 | N2HET[17] |
8 | 111 | N2HET[19] |
NOTE
For ADEVT, N2HET trigger sources, the connection to the MibADC module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad, or by driving the function from an external trigger source as input. If the mux controller module is used to select different functionality instead of ADEVT or N2HET[x], care must be taken to disable these signals from triggering conversions; there is no multiplexing on input connections.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
ADREFHI | A-to-D high-voltage reference source | ADREFLO | VCCAD | V |
ADREFLO | A-to-D low-voltage reference source | VSSAD | ADREFHI | V |
VAI | Analog input voltage | ADREFLO | ADREFHI | V |
IAIC | Analog input clamp current (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3) |
–2 | 2 | mA |
PARAMETER | DESCRIPTION/CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Rmux | Analog input mux on-resistance | See Figure 7-1 | 95 | 250 | Ω | ||
Rsamp | ADC sample switch on-resistance | See Figure 7-1 | 60 | 250 | Ω | ||
Cmux | Input mux capacitance | See Figure 7-1 | 7 | 16 | pF | ||
Csamp | ADC sample capacitance | See Figure 7-1 | 8 | 13 | pF | ||
IAIL | Analog off-state input leakage current | VCCAD = 3.6 V MAX | VSSAD < VIN < VSSAD + 100 mV | –300 | –1 | 200 | nA |
VSSAD + 100 mV < VIN < VCCAD - 200 mV | –200 | –0.3 | 200 | ||||
VCCAD - 200 mV < VIN < VCCAD | –200 | 1 | 500 | ||||
IAOSB | Analog on-state input bias | VCCAD = 3.6 V MAX | VSSAD < VIN < VSSAD + 100 mV | –8 | 2 | µA | |
VSSAD + 100 mV < VIN < VCCAD - 200 mV | –4 | 2 | |||||
VCCAD - 200 mV < VIN < VCCAD | –4 | 12 | |||||
IADREFHI | ADREFHI input current | ADREFHI = VCCAD, ADREFLO = VSSAD | 3 | mA | |||
ICCAD | Static supply current | Normal operating mode | (2) | mA | |||
ADC core in power-down mode | 5 | µA |
PARAMETER | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|
tc(ADCLK)(2) | Cycle time, MibADC clock | 33 | ns | ||
td(SH)(3) | Delay time, sample and hold time | 200 | ns | ||
td(PU-ADV) | Delay time from ADC power on until first input can be sampled | 1 | µs | ||
12-BIT MODE | |||||
td(C) | Delay time, conversion time | 400 | ns | ||
td(SHC)(1) | Delay time, total sample/hold and conversion time | 600 | ns | ||
10-BIT MODE | |||||
td(C) | Delay time, conversion time | 330 | ns | ||
td(SHC)(1) | Delay time, total sample/hold and conversion time | 530 | ns |
PARAMETER | DESCRIPTION/CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
CR | Conversion range over which specified accuracy is maintained | ADREFHI - ADREFLO | 3 | 3.6 | V | |||
ZSET | Offset Error | Difference between the first ideal transition (from code 000h to 001h) and the actual transition | 10-bit mode | With ADC Calibration | 1 | LSB(1) | ||
Without ADC Calibration | 2 | |||||||
12-bit mode | With ADC Calibration | 2 | ||||||
Without ADC Calibration | 4 | |||||||
FSET | Gain Error | Difference between the last ideal transition (from code FFEh to FFFh) and the actual transition minus offset. | 10-bit mode | 2 | LSB | |||
12-bit mode | 3 | |||||||
EDNL | Differential nonlinearity error | Difference between the actual step width and the ideal value. (See Figure 7-2) |
10-bit mode | ± 1.5 | LSB | |||
12-bit mode | ± 2 | |||||||
EINL | Integral nonlinearity error | Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error. (See Figure 7-3) |
10-bit mode | ± 2 | LSB | |||
12-bit mode | ± 2 | |||||||
ETOT | Total unadjusted error | Maximum value of the difference between an analog value and the ideal midstep value. (See Figure 7-4) | 10-bit mode | With ADC Calibration | ± 2 | LSB | ||
Without ADC Calibration | ± 4 | |||||||
12-bit mode | With ADC Calibration | ± 4 | ||||||
Without ADC Calibration | ± 7 |
The differential nonlinearity error shown in Figure 7-2 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB.
The integral nonlinearity error shown in Figure 7-3 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line.
The absolute accuracy or total error of an MibADC as shown in Figure 7-4 is the maximum value of the difference between an analog value and the ideal midstep value.
The GPIO module on this device supports one port GIOA. The I/O pins are bidirectional and bit-programmable. GIOA supports external interrupt capability.
The GPIO module has the following features:
For information on input and output timings see Section 5.11 and Section 5.12
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O.. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
The N2HET module has the following features:
The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one RAM address may be written while another address is read. The RAM words are 96-bits wide, which are split into three 32-bit fields (program, control, and data).
The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.
PARAMETER | MIN(1)(2) | MAX(1)(2) | UNIT | |
---|---|---|---|---|
1 | Input signal period, PCNT or WCAP for rising edge to rising edge | (hr)(lr) tc(VCLK2) + 2 | 225(hr)(lr)tc(VCLK2) - 2 | ns |
2 | Input signal period, PCNT or WCAP for falling edge to falling edge | (hr) (lr) tc(VCLK2) + 2 | 225 (hr)(lr) tc(VCLK2) - 2 | ns |
3 | Input signal high phase, PCNT or WCAP for rising edge to falling edge | 2(hr) tc(VCLK2) + 2 | 225 (hr)(lr) tc(VCLK2) - 2 | ns |
4 | Input signal low phase, PCNT or WCAP for falling edge to rising edge | 2(hr) tc(VCLK2) + 2 | 225 (hr)(lr) tc(VCLK2) - 2 | ns |
N2HET[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure the frequency of the pulse-width modulated (PWM) signal on N2HET[31].
N2HET[31] can be configured to be an internal-only channel. That is, the connection to the DCC module is made directly from the output of the N2HET module (from the input of the output buffer).
For more information on DCC, see Section 6.6.3.
Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET module provides this capability through the "Pin Disable" input signal. This signal, when driven low, causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated.
For more details on the "N2HET Pin Disable" feature, see the device-specific Technical Reference Manual listed in Section 8.2.1.
GIOA[5] and EQEPERR are connected to the "Pin Disable" input for N2HET. In the case of GIOA[5] connection, this connection is made from the output of the input buffer. In the case of EQEPERR, the EQEPERR output signal is asserted in the event of a phase error. This signal is inverted and double-synchronized to VCLK2 for input into the N2HET PIN_nDISABLE port.
The PIN_nDISABLE port input source is selectable between the GIOA[5] and EQEPERR sources. This is achieved through the PINMMR9[1:0] bits.
A High-End Timer Transfer Unit (N2HET) can perform DMA type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the N2HET.
MODULES | REQUEST SOURCE | HTU REQUEST |
---|---|---|
N2HET | HTUREQ[0] | HTU DCP[0] |
N2HET | HTUREQ[1] | HTU DCP[1] |
N2HET | HTUREQ[2] | HTU DCP[2] |
N2HET | HTUREQ[3] | HTU DCP[3] |
N2HET | HTUREQ[4] | HTU DCP[4] |
N2HET | HTUREQ[5] | HTU DCP[5] |
N2HET | HTUREQ[6] | HTU DCP[6] |
N2HET | HTUREQ[7] | HTU DCP[7] |
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.
Features of the DCAN module include:
For more information on the DCAN, see the device-specific Technical Reference Manual listed in Section 8.2.1.
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
td(CANnTX) | Delay time, transmit shift register to CANnTX pin(1) | 15 | ns | |
td(CANnRX) | Delay time, CANnRX pin to receive shift register | 5 | ns |
The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.
The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-line.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-master/multiple-slave with a message identification for multicast transmission between any network nodes.
The following are features of the LIN module:
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers, and ADCs.
Both Standard and MibSPI modules have the following features:
MibSPIx/SPIx | I/Os |
---|---|
MibSPI1 | MIBSPI1SIMO[0], MIBSPI1SOMI[0], MIBSPI1CLK, MIBSPI1nCS[3:0], MIBSPI1nENA |
SPI2 | SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[0] |
SPI3 | SPI3SIMO, SPI3SOMI, SPI3CLK, SPI3nENA, SPI3nCS[0] |
The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of four parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field, and a 16-bit status field. The Multibuffer RAM can be partitioned into multiple transfer group with variable number of buffers each.
Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event and a trigger source can be chosen. A trigger event can be, for example, a rising edge or a permanent low level at a selectable trigger source. Up to 15 trigger sources are available which can be used by each transfer group. These trigger options are listed in Table 7-12.
EVENT NO. | TGxCTRL TRIGSRC[3:0] | TRIGGER |
---|---|---|
Disabled | 0000 | No trigger source |
EVENT0 | 0001 | GIOA[0] |
EVENT1 | 0010 | GIOA[1] |
EVENT2 | 0011 | GIOA[2] |
EVENT3 | 0100 | GIOA[3] |
EVENT4 | 0101 | GIOA[4] |
EVENT5 | 0110 | GIOA[5] |
EVENT6 | 0111 | GIOA[6] |
EVENT7 | 1000 | GIOA[7] |
EVENT8 | 1001 | N2HET[8] |
EVENT9 | 1010 | N2HET[10] |
EVENT10 | 1011 | N2HET[12] |
EVENT11 | 1100 | N2HET[14] |
EVENT12 | 1101 | N2HET[16] |
EVENT13 | 1110 | N2HET[18] |
EVENT14 | 1111 | Internal Tick counter |
NOTE
For N2HET trigger sources, the connection to the MibSPI1 module trigger input is made from the input side of the output buffer (at the N2HET module boundary). This way, a trigger condition can be generated even if the N2HET signal is not selected to be output on the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin, or by driving the GIOx pin from an external trigger source.
NO. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tc(SPC)M | Cycle time, SPICLK(4) | 40 | 256tc(VCLK) | ns | |
2(5) | tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 0) | 0.5tc(SPC)M – tr(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns | |
tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 1) | 0.5tc(SPC)M – tf(SPC)M – 3 | 0.5tc(SPC)M + 3 | |||
3(5) | tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – tf(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns | |
tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – tr(SPC)M – 3 | 0.5tc(SPC)M + 3 | |||
4(5) | td(SPCH-SIMO)M | Delay time, SPISIMO valid before SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – 6 | ns | ||
td(SPCL-SIMO)M | Delay time, SPISIMO valid before SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – 6 | ||||
5(5) | tv(SPCL-SIMO)M | Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – tf(SPC) – 4 | ns | ||
tv(SPCH-SIMO)M | Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – tr(SPC) – 4 | ||||
6(5) | tsu(SOMI-SPCL)M | Setup time, SPISOMI before SPICLK low (clock polarity = 0) | tf(SPC) + 2.2 | ns | ||
tsu(SOMI-SPCH)M | Setup time, SPISOMI before SPICLK high (clock polarity = 1) | tr(SPC) + 2.2 | ||||
7(5) | th(SPCL-SOMI)M | Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) | 10 | ns | ||
th(SPCH-SOMI)M | Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) | 10 | ||||
8(6) | tC2TDELAY | Setup time CS active until SPICLK high (clock polarity = 0) | CSHOLD = 0 | C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 | (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 | ns |
CSHOLD = 1 | C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 | (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 | ||||
Setup time CS active until SPICLK low (clock polarity = 1) | CSHOLD = 0 | C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 | (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 | ns | ||
CSHOLD = 1 | C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 | (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 | ||||
9(6) | tT2CDELAY | Hold time SPICLK low until CS inactive (clock polarity = 0) | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) - 7 | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 | ns | |
Hold time SPICLK high until CS inactive (clock polarity = 1) | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) - 7 | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11 | ns | |||
10 | tSPIENA | SPIENAn Sample point | (C2TDELAY+1) * tc(VCLK) - tf(SPICS) – 29 | (C2TDELAY+1)*tc(VCLK) | ns | |
11 | tSPIENAW | SPIENAn Sample point from write to buffer | (C2TDELAY+2)*tc(VCLK) | ns |
NO. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tc(SPC)M | Cycle time, SPICLK (4) | 40 | 256tc(VCLK) | ns | |
2(5) | tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 0) | 0.5tc(SPC)M – tr(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns | |
tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 1) | 0.5tc(SPC)M – tf(SPC)M – 3 | 0.5tc(SPC)M + 3 | |||
3(5) | tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – tf(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns | |
tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – tr(SPC)M – 3 | 0.5tc(SPC)M + 3 | |||
4(5) | tv(SIMO-SPCH)M | Valid time, SPICLK high after SPISIMO data valid (clock polarity = 0) | 0.5tc(SPC)M – 6 | ns | ||
tv(SIMO-SPCL)M | Valid time, SPICLK low after SPISIMO data valid (clock polarity = 1) | 0.5tc(SPC)M – 6 | ||||
5(5) | tv(SPCH-SIMO)M | Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) | 0.5tc(SPC)M – tr(SPC) – 4 | ns | ||
tv(SPCL-SIMO)M | Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) | 0.5tc(SPC)M – tf(SPC) – 4 | ||||
6(5) | tsu(SOMI-SPCH)M | Setup time, SPISOMI before SPICLK high (clock polarity = 0) | tr(SPC) + 2.2 | ns | ||
tsu(SOMI-SPCL)M | Setup time, SPISOMI before SPICLK low (clock polarity = 1) | tf(SPC) + 2.2 | ||||
7(5) | tv(SPCH-SOMI)M | Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) | 10 | ns | ||
tv(SPCL-SOMI)M | Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) | 10 | ||||
8(6) | tC2TDELAY | Setup time CS active until SPICLK high (clock polarity = 0) | CSHOLD = 0 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) – 7 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 | ns |
CSHOLD = 1 | 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) – 7 | 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 | ||||
Setup time CS active until SPICLK low (clock polarity = 1) | CSHOLD = 0 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) – 7 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 | ns | ||
CSHOLD = 1 | 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) – 7 | 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 | ||||
9(6) | tT2CDELAY | Hold time SPICLK low until CS inactive (clock polarity = 0) | T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) - 7 | T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 | ns | |
Hold time SPICLK high until CS inactive (clock polarity = 1) | T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) - 7 | T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11 | ns | |||
10 | tSPIENA | SPIENAn Sample Point | (C2TDELAY+1)* tc(VCLK) - tf(SPICS) – 29 | (C2TDELAY+1)*tc(VCLK) | ns | |
11 | tSPIENAW | SPIENAn Sample point from write to buffer | (C2TDELAY+2)*tc(VCLK) | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tc(SPC)S | Cycle time, SPICLK(5) | 40 | ns | |
2(6) | tw(SPCH)S | Pulse duration, SPICLK high (clock polarity = 0) | 14 | ns | |
tw(SPCL)S | Pulse duration, SPICLK low (clock polarity = 1) | 14 | |||
3(6) | tw(SPCL)S | Pulse duration, SPICLK low (clock polarity = 0) | 14 | ns | |
tw(SPCH)S | Pulse duration, SPICLK high (clock polarity = 1) | 14 | |||
4(6) | td(SPCH-SOMI)S | Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) | trf(SOMI) + 20 | ns | |
td(SPCL-SOMI)S | Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) | trf(SOMI) + 20 | |||
5(6) | th(SPCH-SOMI)S | Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) | 2 | ns | |
th(SPCL-SOMI)S | Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) | 2 | |||
6(6) | tsu(SIMO-SPCL)S | Setup time, SPISIMO before SPICLK low (clock polarity = 0) | 4 | ns | |
tsu(SIMO-SPCH)S | Setup time, SPISIMO before SPICLK high (clock polarity = 1) | 4 | |||
7(6) | th(SPCL-SIMO)S | Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0) | 2 | ns | |
th(SPCH-SIMO)S | Hold time, SPISIMO data valid after S PICLK high (clock polarity = 1) | 2 | |||
8 | td(SPCL-SENAH)S | Delay time, SPIENAn high after last SPICLK low (clock polarity = 0) | 1.5tc(VCLK) | 2.5tc(VCLK)+tr(ENAn)+ 22 | ns |
td(SPCH-SENAH)S | Delay time, SPIENAn high after last SPICLK high (clock polarity = 1) | 1.5tc(VCLK) | 2.5tc(VCLK)+ tr(ENAn) + 22 | ||
9 | td(SCSL-SENAL)S | Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) | tf(ENAn) | tc(VCLK)+tf(ENAn)+27 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1 | tc(SPC)S | Cycle time, SPICLK(5) | 40 | ns | |
2(6) | tw(SPCH)S | Pulse duration, SPICLK high (clock polarity = 0) | 14 | ns | |
tw(SPCL)S | Pulse duration, SPICLK low (clock polarity = 1) | 14 | |||
3(6) | tw(SPCL)S | Pulse duration, SPICLK low (clock polarity = 0) | 14 | ns | |
tw(SPCH)S | Pulse duration, SPICLK high (clock polarity = 1) | 14 | |||
4(6) | td(SOMI-SPCL)S | Dealy time, SPISOMI data valid after SPICLK low (clock polarity = 0) | trf(SOMI) + 20 | ns | |
td(SOMI-SPCH)S | Delay time, SPISOMI data valid after SPICLK high (clock polarity = 1) | trf(SOMI) + 20 | |||
5(6) | th(SPCL-SOMI)S | Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) | 2 | ns | |
th(SPCH-SOMI)S | Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) | 2 | |||
6(6) | tsu(SIMO-SPCH)S | Setup time, SPISIMO before SPICLK high (clock polarity = 0) | 4 | ns | |
tsu(SIMO-SPCL)S | Setup time, SPISIMO before SPICLK low (clock polarity = 1) | 4 | |||
7(6) | tv(SPCH-SIMO)S | High time, SPISIMO data valid after SPICLK high (clock polarity = 0) | 2 | ns | |
tv(SPCL-SIMO)S | High time, SPISIMO data valid after SPICLK low (clock polarity = 1) | 2 | |||
8 | td(SPCH-SENAH)S | Delay time, SPIENAn high after last SPICLK high (clock polarity = 0) | 1.5tc(VCLK) | 2.5tc(VCLK)+tr(ENAn) + 22 | ns |
td(SPCL-SENAH)S | Delay time, SPIENAn high after last SPICLK low (clock polarity = 1) | 1.5tc(VCLK) | 2.5tc(VCLK)+tr(ENAn) + 22 | ||
9 | td(SCSL-SENAL)S | Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) | tf(ENAn) | tc(VCLK)+tf(ENAn)+ 27 | ns |
10 | td(SCSL-SOMI)S | Delay time, SOMI valid after SPICSn low (if new data has been written to the SPI buffer) | tc(VCLK) | 2tc(VCLK)+trf(SOMI)+ 28 | ns |
Figure 7-14 shows the eQEP module interconnections on the device.
The device level control of the eQEP clock is accomplished through the enable/disable of the VCLK clock domain for eQEP only. This is realized using bit 9 of the CLKDDIS register. The eQEP clock source is enabled by default.
The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection multiplexor. As shown in Figure 7-14, the output of this selection multiplexor is inverted and connected to the N2HET module. This connection allows the application to define the response to a phase error indicated by the eQEP modules.
The input connections to each of the eQEP modules can be selected between a double-VCLK-synchronized input or a double-VCLK-synchronized and filtered input, as shown in Table 7-17.
INPUT SIGNAL | CONTROL FOR DOUBLE-SYNCHRONIZED CONNECTION TO eQEPx |
CONTROL FOR DOUBLE-SYNCHRONIZED AND FILTERED CONNECTION TO eQEPx |
---|---|---|
eQEPA | PINMMR8[0] = 1 | PINMMR8[0] = 0 and PINMMR8[1] = 1 |
eQEPB | PINMMR8[8] = 1 | PINMMR8[8] = 0 and PINMMR8[9] = 1 |
eQEPI | PINMMR8[16] = 1 | PINMMR8[16] = 0 and PINMMR8[17] = 1 |
eQEPS | PINMMR8[24] = 1 | PINMMR8[24] = 0 and PINMMR8[25] = 1 |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
tw(QEPP) | QEP input period | Synchronous | 2 tc(VCLK) | cycles | |
Synchronous, with input filter | 2 tc(VCLK) + filter width | cycles | |||
tw(INDEXH) | QEP Index Input High Time | Synchronous | 2 tc(VCLK) | cycles | |
Synchronous, with input filter | 2 tc(VCLK) + filter width | cycles | |||
tw(INDEXL) | QEP Index Input Low Time | Synchronous | 2 tc(VCLK) | cycles | |
Synchronous, with input filter | 2 tc(VCLK) + filter width | cycles | |||
tw(STROBH) | QEP Strobe Input High Time | Synchronous | 2 tc(VCLK) | cycles | |
Synchronous, with input filter | 2 tc(VCLK) + filter width | cycles | |||
tw(STROBL) | QEP Strobe Input Low Time | Synchronous | 2 tc(VCLK) | cycles | |
Synchronous, with input filter | 2 tc(VCLK) + filter width | cycles |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
td(CNTR)xin | Delay time, external clock to counter increment | 4 tc(VCLK) | cycles | |
td(PCS-OUT)QEP | Delay time, QEP input edge to position compare sync output | 6 tc(VCLK) | cycles |