SPNS180B September   2012  – June 2015 RM42L432

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Terminal Functions
      1. 4.2.1  High-End Timer (N2HET)
      2. 4.2.2  Enhanced Quadrature Encoder Pulse Modules (eQEP)
      3. 4.2.3  General-Purpose Input/Output (GPIO)
      4. 4.2.4  Controller Area Network Interface Modules (DCAN1, DCAN2)
      5. 4.2.5  Multibuffered Serial Peripheral Interface (MibSPI1)
      6. 4.2.6  Standard Serial Peripheral Interface (SPI2)
      7. 4.2.7  Local Interconnect Network Controller (LIN)
      8. 4.2.8  Multibuffered Analog-to-Digital Converter (MibADC)
      9. 4.2.9  System Module
      10. 4.2.10 Error Signaling Module (ESM)
      11. 4.2.11 Main Oscillator
      12. 4.2.12 Test/Debug Interface
      13. 4.2.13 Flash
      14. 4.2.14 Core Supply
      15. 4.2.15 I/O Supply
      16. 4.2.16 Core and I/O Supply Ground Reference
    3. 4.3 Output Multiplexing and Control
      1. 4.3.1 Notes on Output Multiplexing
      2. 4.3.2 General Rules for Multiplexing Control Registers
    4. 4.4 Special Multiplexed Options
      1. 4.4.1 Filtering for eQEP Inputs
        1. 4.4.1.1 eQEPA Input
        2. 4.4.1.2 eQEPB Input
        3. 4.4.1.3 eQEPI Input
        4. 4.4.1.4 eQEPS Input
      2. 4.4.2 N2HET PIN_nDISABLE Input Port
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Thermal Resistance Characteristics for PZ
    9. 5.9  Input/Output Electrical Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
  6. 6System Information and Electrical Specifications
    1. 6.1  Voltage Monitor Characteristics
      1. 6.1.1 Important Considerations
      2. 6.1.2 Voltage Monitor Operation
      3. 6.1.3 Supply Filtering
    2. 6.2  Power Sequencing and Power-On Reset
      1. 6.2.1 Power-Up Sequence
      2. 6.2.2 Power-Down Sequence
      3. 6.2.3 Power-On Reset: nPORRST
        1. 6.2.3.1 nPORRST Electrical and Timing Requirements
    3. 6.3  Warm Reset (nRST)
      1. 6.3.1 Causes of Warm Reset
      2. 6.3.2 nRST Timing Requirements
    4. 6.4  ARM Cortex-R4 CPU Information
      1. 6.4.1 Summary of ARM Cortex-R4 CPU Features
      2. 6.4.2 ARM Cortex-R4 CPU Features Enabled by Software
      3. 6.4.3 Dual Core Implementation
      4. 6.4.4 Duplicate clock tree after GCLK
      5. 6.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety
      6. 6.4.6 CPU Self-Test
        1. 6.4.6.1 Application Sequence for CPU Self-Test
        2. 6.4.6.2 CPU Self-Test Clock Configuration
        3. 6.4.6.3 CPU Self-Test Coverage
    5. 6.5  Clocks
      1. 6.5.1 Clock Sources
        1. 6.5.1.1 Main Oscillator
          1. 6.5.1.1.1 Timing Requirements for Main Oscillator
        2. 6.5.1.2 Low-Power Oscillator
          1. 6.5.1.2.1 Features
          2. 6.5.1.2.2 LPO Electrical and Timing Specifications
        3. 6.5.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.5.1.3.1 Block Diagram
          2. 6.5.1.3.2 PLL Timing Specifications
      2. 6.5.2 Clock Domains
        1. 6.5.2.1 Clock Domain Descriptions
        2. 6.5.2.2 Mapping of Clock Domains to Device Modules
      3. 6.5.3 Clock Test Mode
    6. 6.6  Clock Monitoring
      1. 6.6.1 Clock Monitor Timings
      2. 6.6.2 External Clock (ECLK) Output Functionality
      3. 6.6.3 Dual Clock Comparator
        1. 6.6.3.1 Features
        2. 6.6.3.2 Mapping of DCC Clock Source Inputs
    7. 6.7  Glitch Filters
    8. 6.8  Device Memory Map
      1. 6.8.1 Memory Map Diagram
      2. 6.8.2 Memory Map Table
      3. 6.8.3 Master/Slave Access Privileges
    9. 6.9  Flash Memory
      1. 6.9.1 Flash Memory Configuration
      2. 6.9.2 Main Features of Flash Module
      3. 6.9.3 ECC Protection for Flash Accesses
      4. 6.9.4 Flash Access Speeds
    10. 6.10 Flash Program and Erase Timings for Program Flash
    11. 6.11 Flash Program and Erase Timings for Data Flash
    12. 6.12 Tightly Coupled RAM Interface Module
      1. 6.12.1 Features
      2. 6.12.2 TCRAMW ECC Support
    13. 6.13 Parity Protection for Accesses to peripheral RAMs
    14. 6.14 On-Chip SRAM Initialization and Testing
      1. 6.14.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.14.1.1 Features
        2. 6.14.1.2 PBIST RAM Groups
      2. 6.14.2 On-Chip SRAM Auto Initialization
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
    17. 6.17 Error Signaling Module
      1. 6.17.1 Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset / Abort / Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1 Peripheral Legend
    2. 7.2 Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 MIBADC Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3 General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4 Enhanced High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET Checking
        1. 7.4.4.1 Output Monitoring using Dual Clock Comparator (DCC)
      5. 7.4.5 Disabling N2HET Outputs
      6. 7.4.6 High-End Timer Transfer Unit (N2HET)
        1. 7.4.6.1 Features
        2. 7.4.6.2 Trigger Connections
    5. 7.5 Controller Area Network (DCAN)
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
    6. 7.6 Local Interconnect Network Interface (LIN)
      1. 7.6.1 LIN Features
    7. 7.7 Multibuffered / Standard Serial Peripheral Interface
      1. 7.7.1 Features
      2. 7.7.2 MibSPI Transmit and Receive RAM Organization
      3. 7.7.3 MibSPI Transmit Trigger Events
        1. 7.7.3.1 MIBSPI1 Event Trigger Hookup
      4. 7.7.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.7.5 SPI Slave Mode I/O Timings
    8. 7.8 Enhanced Quadrature Encoder (eQEP)
      1. 7.8.1 Clock Enable Control for eQEPx Modules
      2. 7.8.2 Using eQEPx Phase Error
      3. 7.8.3 Input Connections to eQEPx Modules
      4. 7.8.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Getting Started
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
    7. 8.7 Device Identification Code Register
    8. 8.8 Die Identification Registers
    9. 8.9 Module Certifications
      1. 8.9.1 DCAN Certification
      2. 8.9.2 LIN Certifications
        1. 8.9.2.1 LIN Master Mode
        2. 8.9.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.9.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Addendum
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PZ|100
サーマルパッド・メカニカル・データ
発注情報

5 Specifications

5.1 Absolute Maximum Ratings(1)

Over Operating Free-Air Temperature Range
MIN MAX UNIT
Supply voltage VCC(2) –0.3 1.43 V
VCCIO, VCCP(2) –0.3 4.6
VCCAD –0.3 3.6
Input voltage All input pins –0.3 4.6 V
ADC input pins –0.3 4.6
Input clamp current IIK (VI < 0 or VI > VCCIO)
All pins, except ADIN		 –20 20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN		 –10 10
Total –40 40
Operating free-air temperature, TA –40 105 °C
Operating junction temperature, TJ –40 130 °C
Latch-up performance I-test, All I/O pins –100 100 mA
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated grounds.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge (ESD) performance: Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1) ±2 kV
Charged Device Model (CDM), per JESD22-C101(2) All pins ±250 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Power-On Hours (POH)(1)(2)

NOMINAL CORE VOLTAGE (VCC) JUNCTION
TEMPERATURE (Tj) 		LIFETIME POH
1.2 105ºC 100K
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application Report (SPNA207).

5.4 Recommended Operating Conditions(1)

MIN NOM MAX UNIT
VCC Digital logic supply voltage (Core) 1.14 1.2 1.32 V
VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V
VCCAD / VADREFHI MibADC supply voltage / A-to-D high-voltage reference source 3 3.3 3.6 V
VCCP Flash pump supply voltage 3 3.3 3.6 V
VSS Digital logic supply ground 0 V
VSSAD / VADREFLO MibADC supply ground / A-to-D low-voltage reference source –0.1 0.1 V
VSLEW Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies 1 V/µs
TA Operating free-air temperature –40 105 °C
TJ Operating junction temperature(2) –40 130 °C
(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.

5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains

Table 5-1 Clock Domains Timing Specifications

PARAMETER CONDITIONS MIN MAX UNIT
fHCLK HCLK - System clock frequency 100 MHz
fGCLK GCLK - CPU clock frequency (ratio fGCLK : fHCLK = 1:1) fHCLK MHz
fVCLK VCLK - Primary peripheral clock frequency 100 MHz
fVCLK2 VCLK2 - Secondary peripheral clock frequency 100 MHz
fVCLKA1 VCLKA1 - Primary asynchronous peripheral clock frequency 100 MHz
fRTICLK RTICLK - clock frequency fVCLK MHz

5.6 Wait States Required

The TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required. There are no registers which need to be programmed for RAM wait states.

The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode.The flash supports a maximum CPU clock speed of 100 MHz in pipelined mode with no address wait states and one data wait state.

The proper wait states should be set in the register fields Address Setup Wait State Enable (ASWSTEN 0xFFF87000[4]), Random Wait states (RWAIT 0xFFF87000[11:8]), and Emulation Wait states (EWAIT 0xFFF872B8[19:16]) as shown in Figure 5-1.

RM42L432 wait_states_f3_pns186.gifFigure 5-1 Wait States Scheme

The flash wrapper defaults to nonpipelined mode with address wait states disabled, ASWSTEN=0; the main memory random-read data wait state, RWAIT=1; and the emulation memory random-read wait states, EWAIT=1.

5.7 Power Consumption

Over Recommended Operating Conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC VCC digital supply current (operating mode)

fHCLK = 100 MHz

fVCLK = 100 MHz, Flash in pipelined mode, VCCmax

150(2) mA
VCC digital supply current (LBIST mode) LBIST clock rate = 50 MHz 165(3)(4)
VCC digital supply current (PBIST mode) PBIST ROM clock frequency = 100 MHz 150(3)(4)
ICCREFHI ADREFHI supply current (operating mode) ADREFHImax 3 mA
ICCAD VCCAD supply current (operating mode) VCCADmax 45(1) mA
ICCIO VCCIO digital supply current (operating mode) No DC load, VCCmax
ICCP VCCP pump supply current Read mode
ICCP, ICCIO,ICCAD 3.3-V supply current Read from one bank and program or erase another, VCCPmax 65(1) mA
(1) Maximum current requirement of the three combined supplies
(2) The maximum ICC, value can be derated
  • linearly with voltage
  • by 0.76 mA/MHz for lower operating frequency when fHCLK= fVCLK
  • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.

    36 - 0.001 0.026TJK
(3) The maximum ICC, value can be derated
  • linearly with voltage
  • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.

    36 - 0.001 0.026TJK
(4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the device and the voltage regulator

5.8 Thermal Resistance Characteristics for PZ

Table 5-2 shows the thermal resistance characteristics for the PQFP - PZ mechanical packages.

Table 5-2 Thermal Resistance Characteristics
(S-PQFP Package) [PZ]

PARAMETER °C/W
RθJA 48
RθJC 5

5.9 Input/Output Electrical Characteristics(1)

Over Recommended Operating Conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vhys Input hysteresis All inputs 180 mV
VIL Low-level input voltage All inputs(2) –0.3 0.8 V
VIH High-level input voltage All inputs(2) 2 VCCIO + 0.3 V
VOL Low-level output voltage IOL = IOLmax 0.2 VCCIO V
IOL = 50 µA, standard output mode 0.2
VOH High-level output voltage IOH = IOHmax 0.8 VCCIO V
IOH = 50 µA, standard output mode VCCIO - 0.3
IIC Input clamp current (I/O pins) VI < VSSIO - 0.3 or VI > VCCIO + 0.3 –3.5 3.5 mA
II Input current (I/O pins) IIH 20-µA pulldown VI = VCCIO 5 40 µA
IIH 100-µA pulldown VI = VCCIO 40 195
IIL 20-µA pullup VI = VSS –40 –5
IIL 100-µA pullup VI = VSS –195 –40
All other pins No pullup or pulldown –1 1
CI Input capacitance 2 pF
CO Output capacitance 3 pF
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) This does not apply to the nPORRST pin.

5.10 Output Buffer Drive Strengths

Table 5-3 Output Buffer Drive Strengths

LOW-LEVEL OUTPUT CURRENT,
IOL for VI=VOLmax
or
HIGH-LEVEL OUTPUT CURRENT,
IOH for VI=VOHmin		 SIGNALS
8 mA

EQEPI, EQEPS,

TMS, TDI, TDO, RTCK,

nERROR
4 mA

TEST,

MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, SPI3CLK, SPI3SIMO, SPI3SOMI,

nRST
2 mA zero-dominant

AD1EVT,

CAN1RX, CAN1TX, CAN2RX, CAN2TX,

GIOA[0-7],

LINRX, LINTX,

MIBSPI1nCS[0-3], MIBSPI1nENA

N2HET[0], N2HET[2], N2HET[4], N2HET[6], N2HET[8], N2HET[10], N2HET[12], N2HET[14], N2HET[16], N2HET[18], N2HET[22], N2HET[24],

SPI2nCS[0-3], SPI3nENA, SPI3nCS[0]
selectable 8 mA/ 2 mA

ECLK,

SPI2CLK, SPI2SIMO, SPI2SOMI

The default output buffer drive strength is 8 mA for these signals.

Table 5-4 Selectable 8 mA/ 2 mA Control

SIGNAL CONTROL BIT ADDRESS 8 mA 2 mA
ECLK SYSPC10[0] 0xFFFF FF78 0 1
SPI2CLK SPI2PC9[9] 0xFFF7 F668 0 1
SPI2SIMO SPI2PC9[10] 0xFFF7 F668 0 1
SPI2SOMI SPI2PC9[11](1) 0xFFF7 F668 0 1
(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these 2 bits differ, SPI2PC9[11] determines the drive strength.

5.11 Input Timings

RM42L432 ttl_inputs_pns160.gifFigure 5-2 TTL-Level Inputs

Table 5-5 Timing Requirements for Inputs(1)

MIN MAX UNIT
tpw Input minimum pulse width tc(VCLK) + 10(2) ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown in Figure 5-2 is only valid for pin used in GIO mode.

5.12 Output Timings

Table 5-6 Switching Characteristics for Output Timings versus Load Capacitance (CL)

PARAMETER MIN MAX UNIT
Rise time, tr 8-mA pins CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, tf CL = 15 pF 2.5
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, tr 4-mA pins CL = 15 pF 5.6 ns
CL = 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Fall time, tf CL = 15 pF 5.6
CL= 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Rise time, tr 2-mA-z pins CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, tf CL = 15 pF 8
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Rise time, tr Selectable 8-mA/ 2-mA-z pins 8-mA mode CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, tf CL = 15 pF 2.5
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, tr 2-mA-z mode CL = 15 pF 8
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, tf CL = 15 pF 8
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
RM42L432 cmos_outputs_pns160.gifFigure 5-3 CMOS-Level Outputs

Table 5-7 Timing Requirements for Outputs(1)

PARAMETER MIN MAX UNIT
td(parallel_out) Delay between low-to-high, or high-to-low transition of general-purpose output signals that can be configured by an application in parallel, for example, all signals in a GIOA port, or all N2HET signals. 5 ns
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check Table 5-3 for output buffer drive strength information on each signal.