6.1.1 Important Considerations

• The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in reset when the voltage supplies are out of range.
• The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.

6.1.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good I/O signal (PGIO) on the device. During power up or power down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during the power up or power down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.2.3.1 for the timing information on this glitch filter.

6.1.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

Table 6-2 shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum specification cannot be filtered.

6.2.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (for more details, see Table 6-4), core voltage rising above the minimum core supply threshold, and the release of power-on reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start-up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order.

During power up, the device goes through the sequential phases listed in Table 6-3.

The CPU reset is released at the end of this sequence and fetches the first instruction from address 0x00000000.

6.2.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.2.3 Power-On Reset: nPORRST

This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

6.2.3.1 nPORRST Electrical and Timing Requirements

Table 6-4 Electrical Requirements for nPORRST

NO.	PARAMETER		MIN	MAX	UNIT
	VCCPORL	VCC low supply level when nPORRST must be active during power up		0.5	V
	VCCPORH	VCC high supply level when nPORRST must remain active during power up and become active during power down	1.14		V
	VCCIOPORL	VCCIO / VCCP low supply level when nPORRST must be active during power up		1.1	V
	VCCIOPORH	VCCIO / VCCP high supply level when nPORRST must remain active during power up and become active during power down	3.0		V
	VIL(PORRST)	Low-level input voltage of nPORRST VCCIO > 2.5 V		0.2 * VCCIO	V
		Low-level input voltage of nPORRST VCCIO < 2.5 V		0.5	V
3	tsu(PORRST)	Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power up	0		ms
6	th(PORRST)	Hold time, nPORRST active after VCC > VCCPORH	1		ms
7	tsu(PORRST)	Setup time, nPORRST active before VCC < VCCPORH during power down	2		µs
8	th(PORRST)	Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH	1		ms
9	th(PORRST)	Hold time, nPORRST active after VCC < VCCPORL	0		ms
	tf(nPORRST)	Filter time nPORRST pin; Pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset.	475	2000	ns

Figure 6-1 nPORRST Timing Diagram

6.3.1 Causes of Warm Reset

6.3.2 nRST Timing Requirements

6.4.1 Summary of ARM Cortex-R4 CPU Features

The features of the ARM Cortex-R4 CPU include:

• An integer unit with integral Embedded ICE-RT logic.
• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
• Dynamic branch prediction with a global history buffer, and a 4-entry return stack
• Low interrupt latency.
• Nonmaskable interrupt.
• A Harvard Level one (L1) memory system with:
  • Tightly Coupled Memory (TCM) interfaces with support for error correction or parity checking memories
  • ARMv7-R architecture Memory Protection Unit (MPU) with 8 regions
• Dual core logic for fault detection in safety-critical applications.
• An L2 memory interface:
  • Single 64-bit master AXI interface
  • 64-bit slave AXI interface to TCM RAM blocks
• A debug interface to a CoreSight Debug Access Port (DAP).
• Six Hardware Breakpoints
• Two Watchpoints
• A Perfomance Monitoring Unit (PMU)
• A Vectored Interrupt Controller (VIC) port.

For more information on the ARM Cortex-R4 CPU, see www.arm.com.

6.4.2 ARM Cortex-R4 CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

• ECC On Tightly Coupled Memory (TCM) Accesses
• Hardware Vectored Interrupt (VIC) Port
• Memory Protection Unit (MPU)

6.4.3 Dual Core Implementation

The device has two Cortex-R4 cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock cycles as shown in Figure 6-3.

6.4.4 Duplicate clock tree after GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.

6.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety

This device has two ARM Cortex-R4 CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in Figure 6-3.

Figure 6-3 Dual Core Implementation

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed onto the stack.

6.4.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4 CPU Cores using the Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

• Ability to divide the complete test run into independent test intervals
• Capable of running the complete test or running a few intervals at a time
• Ability to continue from the last executed interval (test set) or to restart from the beginning (first test set)
• Complete isolation of the self-tested CPU core from the rest of the system during the self-test run
• Ability to capture the failure interval number
• Timeout counter for the CPU self-test run as a fail-safe feature

6.5.1 Clock Sources

The table below lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source.

The table also shows the default state of each clock source.

6.5.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes.

TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.

An external oscillator source can be used by connecting a 3.3 V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in Figure 6-4.

Figure 6-4 Recommended Crystal/Clock Connection

6.5.1.1.1 Timing Requirements for Main Oscillator

Table 6-9 Timing Requirements for Main Oscillator

PARAMETER		MIN	TYP	MAX	UNIT
tc(OSC)	Cycle time, OSCIN (when using a sine-wave input)	50		200	ns
tc(OSC_SQR)	Cycle time, OSCIN, (when input to the OSCIN is a square wave )	50		200	ns
tw(OSCIL)	Pulse duration, OSCIN low (when input to the OSCIN is a square wave)	15			ns
tw(OSCIH)	Pulse duration, OSCIN high (when input to the OSCIN is a square wave)	15			ns

6.5.1.2 Low-Power Oscillator

The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO.

6.5.1.2.1 Features

The main features of the LPO are:

• Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4 of the Global Clock Module.
• Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source # 5 of the Global Clock Module.
• Provides a comparison clock for the crystal oscillator failure detection circuit.

Figure 6-5 LPO Block Diagram

Figure 6-5 shows a block diagram of the internal reference oscillator. This is an LPO and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.

6.5.1.2.2 LPO Electrical and Timing Specifications

Table 6-10 LPO Specifications

PARAMETER		MIN	TYP	MAX	UNIT
Clock Detection	Oscillator fail frequency - lower threshold, using untrimmed LPO output	1.375	2.4	4.875	MHz
	Oscillator fail frequency - higher threshold, using untrimmed LPO output	22	38.4	78
LPO - HF oscillator (fHFLPO)	Untrimmed frequency	5.5	9	19.5	MHz
	Trimmed frequency	8	9.6	11	MHz
	Start-up time from STANDBY (LPO BIAS_EN High for at least 900 µs)			10	µs
	Cold start-up time			900	µs
LPO - LF oscillator (fLFLPO)	Untrimmed frequency	36	85	180	kHz
	Start-up time from STANDBY (LPO BIAS_EN High for at least 900 µs)			100	µs
	Cold start-up time			2000	µs

6.5.1.3 Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

• Frequency modulation can be optionally superimposed on the synthesized frequency of PLL.
• Configurable frequency multipliers and dividers.
• Built-in PLL Slip monitoring circuit.
• Option to reset the device on a PLL slip detection.

6.5.1.3.1 Block Diagram

Figure 6-6 shows a high-level block diagram of the PLL macro on this microcontroller.

Figure 6-6 PLL Block Diagram

6.5.1.3.2 PLL Timing Specifications

Table 6-11 PLL Timing Specifications

PARAMETER		MIN	MAX	UNIT
fINTCLK	PLL1 Reference Clock frequency	1	20	MHz
fpost_ODCLK	Post-ODCLK – PLL1 Post-divider input clock frequency		400	MHz
fVCOCLK	VCOCLK – PLL1 Output Divider (OD) input clock frequency	150	550	MHz

6.5.2 Clock Domains

6.5.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in the figure below.

Figure 6-7 Device Clock Domains

6.5.3 Clock Test Mode

The RM4x platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET[2] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured through the CLKTEST register in the system module.

6.6.1 Clock Monitor Timings

For more information on LPO and Clock detection, refer to Table 6-10.

Figure 6-8 LPO and Clock Detection, Untrimmed HFLPO

6.6.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic.

6.6.3 Dual Clock Comparator

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC can be configured to use CLK10M as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC to monitor the PLL output clock when VCLK is using the PLL output as its source.

Table 6-16 Glitch Filter Timing Specifications

6.8.1 Memory Map Diagram

Figure 6-9 shows the device memory map.

Figure 6-9 RM42LS432 Memory Map

The Flash memory in all configurations is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000.

6.8.2 Memory Map Table

See Figure 1-1 for a block diagram showing the device interconnects.

6.8.3 Master/Slave Access Privileges

The table below lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed in the "MASTERS" column can access that slave module.

6.9.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

6.9.2 Main Features of Flash Module

• Support for multiple flash banks for program and/or data storage
• Simultaneous read access on a bank while performing program or erase operation on any other bank
• Integrated state machines to automate flash erase and program operations
• Software interface for flash program and erase operations
• Pipelined mode operation to improve instruction access interface bandwidth
• Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4 CPU
  • Error address is captured for host system debugging
• Support for a rich set of diagnostic features

6.9.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance Monitor Control Register, c9.

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN bits of the System Control coprocessor's Auxiliary Control Register, c1.

6.9.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, see Section 5.6.

Table 6-20 Timing Specifications for Program Flash

Table 6-21 Timing Specifications for Data Flash

6.12.1 Features

The features of the Tightly Coupled RAM (TCRAM) module are:

• Acts as slave to the BTCM interface of the Cortex-R4 CPU
• Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code
• Monitors CPU Event Bus and generates single-bit or multibit error interrupts
• Stores addresses for single-bit and multibit errors
• Provides CPU address bus integrity checking by supporting parity checking on the address bus
• Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
• Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved RAM banks and generating independent RAM access control signals to the two banks
• Supports auto-initialization of the RAM banks along with the ECC bits
• No support for bit-wise RAM accesses

6.12.2 TCRAMW ECC Support

The TCRAMW passes on the ECC code for each data read by the Cortex-R4 CPU from the RAM. It also stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The TCRAMW monitors the CPU's event bus and provides registers for indicating single-bit and multibit errors and also for identifying the address that caused the single-bit or multibit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.

For more information see the device Technical Reference Manual.

6.14.1 On-Chip SRAM Self-Test Using PBIST

6.14.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized.

For more information on these registers refer to the device Technical Reference Manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table 6-23.

6.15.1 VIM Features

The VIM module has the following features:

• Supports 96 interrupt channels.
  • Provides programmable priority and enable for interrupt request lines.
• Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
• Provides two software dispatch mechanisms when the CPU VIC port is not used.
  • Index interrupt
  • Register vectored interrupt
• Parity protected vector interrupt table against soft errors.

6.15.2 Interrupt Request Assignments

6.16.1 Features

The RTI module has the following features:

• Two independent 64 bit counter blocks
• Four configurable compares for generating operating system ticks. Each event can be driven by either counter block 0 or counter block 1.
• Fast enabling/disabling of events
• Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block

6.16.2 Block Diagrams

Figure 6-11 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module. Both the counter blocks are identical.

Figure 6-11 Counter Block Diagram

Figure 6-12 shows a typical high-level block diagram for one of the four compares inside the RTI module. Each of the four compares are identical.

Figure 6-12 Compare Block Diagram

6.16.3 Clock Source Options

The RTI module uses the RTICLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTICLK by configuring the RCLKSRC register in the System module at address 0xFFFFFF50. The default source for RTICLK is VCLK.

For more information, on the clock sources see Table 6-8 and Table 6-12.

6.17.1 Features

The features of the Error Signaling Module are:

• 128 interrupt/error channels are supported, divided into 3 different groups
  • 64 channels with maskable interrupt and configurable error pin behavior
  • 32 error channels with nonmaskable interrupt and predefined error pin behavior
  • 32 channels with predefined error pin behavior only
• Error pin to signal severe device failure
• Configurable timebase for error signal
• Error forcing capability

6.17.2 ESM Channel Assignments

The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group it is connected to. Table 6-26 shows the channel assignment for each group.

Table 6-27 Reset/Abort/Error Sources

6.20.1 Block Diagram

The device contains an ICEPICK module to allow JTAG access to the scan chains (see Figure 6-13).

Figure 6-13 Debug Subsystem Block Diagram

6.20.2 Debug Components Memory Map

6.20.3 JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code.

6.20.4 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus:

6.20.5 JTAG Scan Interface Timings

Figure 6-14 JTAG Timing

6.20.6 Advanced JTAG Security Module

This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to the memory content of the device by allowing users to secure the device after programming.

Figure 6-15 AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the UNLOCK signal being asserted, so that the device is now unsecure.

A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing a 0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP) flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the device.

Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents and the Unlock-By-Scan register contents results in the original visible unlock code.

The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).

A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap # 2 of the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in this state.

6.20.7 Boundary Scan Chain

The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module.

Figure 6-16 Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.