SPNS215C February   2014  – June 2016 RM57L843

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
  4. 4 Terminal Configuration and Functions
    1. 4.1 ZWT BGA Package Ball-Map (337 Terminal Grid Array)
    2. 4.2 Terminal Functions
      1. 4.2.1 ZWT Package
        1. 4.2.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.2.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.2.1.3  RAM Trace Port (RTP)
        4. 4.2.1.4  Enhanced Capture Modules (eCAP)
        5. 4.2.1.5  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        6. 4.2.1.6  Enhanced Pulse-Width Modulator Modules (ePWM)
        7. 4.2.1.7  Data Modification Module (DMM)
        8. 4.2.1.8  General-Purpose Input / Output (GIO)
        9. 4.2.1.9  Controller Area Network Controllers (DCAN)
        10. 4.2.1.10 Local Interconnect Network Interface Module (LIN)
        11. 4.2.1.11 Standard Serial Communication Interface (SCI)
        12. 4.2.1.12 Inter-Integrated Circuit Interface Module (I2C)
        13. 4.2.1.13 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        14. 4.2.1.14 Ethernet Controller
        15. 4.2.1.15 External Memory Interface (EMIF)
        16. 4.2.1.16 Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)
        17. 4.2.1.17 System Module Interface
        18. 4.2.1.18 Clock Inputs and Outputs
        19. 4.2.1.19 Test and Debug Modules Interface
        20. 4.2.1.20 Flash Supply and Test Pads
        21. 4.2.1.21 Supply for Core Logic: 1.2-V Nominal
        22. 4.2.1.22 Supply for I/O Cells: 3.3-V Nominal
        23. 4.2.1.23 Ground Reference for All Supplies Except VCCAD
        24. 4.2.1.24 Other Supplies
      2. 4.2.2 Multiplexing
        1. 4.2.2.1 Output Multiplexing
          1. 4.2.2.1.1 Notes on Output Multiplexing
        2. 4.2.2.2 Input Multiplexing
          1. 4.2.2.2.1 Notes on Input Multiplexing
          2. 4.2.2.2.2 General Rules for Multiplexing Control Registers
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Device Recommended Operating Conditions
    5. 5.5  Switching Characteristics over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required - L2 Memories
    7. 5.7  Power Consumption Summary
    8. 5.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 5.9  Thermal Resistance Characteristics for the BGA Package (ZWT)
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1 Input Timings
      2. 5.10.2 Output Timings
  6. 6 System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power-On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R5F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R5F CPU Features
      2. 6.5.2 Dual Core Implementation
      3. 6.5.3 Duplicate Clock Tree After GCLK
      4. 6.5.4 ARM Cortex-R5F CPU Compare Module (CCM) for Safety
        1. 6.5.4.1 Signal Compare Operating Modes
          1. 6.5.4.1.1 Active Compare Lockstep Mode
          2. 6.5.4.1.2 Self-Test Mode
          3. 6.5.4.1.3 Error Forcing Mode
          4. 6.5.4.1.4 Self-Test Error Forcing Mode
        2. 6.5.4.2 Bus Inactivity Monitor
        3. 6.5.4.3 CPU Registers Initialization
      5. 6.5.5 CPU Self-Test
        1. 6.5.5.1 Application Sequence for CPU Self-Test
        2. 6.5.5.2 CPU Self-Test Clock Configuration
        3. 6.5.5.3 CPU Self-Test Coverage
      6. 6.5.6 N2HET STC / LBIST Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase-Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      4. 6.6.4 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
        1. 6.9.4.1 Special Notes on Accesses to Certain Slaves
      5. 6.9.5 MasterID to PCRx
      6. 6.9.6 CPU Interconnect Subsystem SDC MMR Port
      7. 6.9.7 Parameter Overlay Module (POM) Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Flash Program and Erase Timings
        1. 6.10.5.1 Flash Program and Erase Timings for Program Flash
        2. 6.10.5.2 Flash Program and Erase Timings for Data Flash
    11. 6.11 L2RAMW (Level 2 RAM Interface Module)
      1. 6.11.1 L2 SRAM Initialization
    12. 6.12 ECC / Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Read Timing (Asynchronous RAM)
        2. 6.14.2.2 Write Timing (Asynchronous RAM)
        3. 6.14.2.3 EMIF Asynchronous Memory Timing
        4. 6.14.2.4 Read Timing (Synchronous RAM)
        5. 6.14.2.5 Write Timing (Synchronous RAM)
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Generation
      3. 6.15.3 Interrupt Request Assignments
    16. 6.16 ECC Error Event Monitoring and Profiling
      1. 6.16.1 EPC Module Operation
        1. 6.16.1.1 Correctable Error Handling
        2. 6.16.1.2 Uncorrectable Error Handling
    17. 6.17 DMA Controller
      1. 6.17.1 DMA Features
      2. 6.17.2 DMA Transfer Port Assignment
      3. 6.17.3 Default DMA Request Map
      4. 6.17.4 Using a GIO terminal as a DMA Request Input
    18. 6.18 Real-Time Interrupt Module
      1. 6.18.1 Features
      2. 6.18.2 Block Diagrams
      3. 6.18.3 Clock Source Options
      4. 6.18.4 Network Time Synchronization Inputs
    19. 6.19 Error Signaling Module
      1. 6.19.1 ESM Features
      2. 6.19.2 ESM Channel Assignments
    20. 6.20 Reset / Abort / Error Sources
    21. 6.21 Digital Windowed Watchdog
    22. 6.22 Debug Subsystem
      1. 6.22.1  Block Diagram
      2. 6.22.2  Debug Components Memory Map
      3. 6.22.3  Embedded Cross Trigger
      4. 6.22.4  JTAG Identification Code
      5. 6.22.5  Debug ROM
      6. 6.22.6  JTAG Scan Interface Timings
      7. 6.22.7  Advanced JTAG Security Module
      8. 6.22.8  Embedded Trace Macrocell (ETM-R5)
        1. 6.22.8.1 ETM TRACECLKIN Selection
        2. 6.22.8.2 Timing Specifications
      9. 6.22.9  RAM Trace Port (RTP)
        1. 6.22.9.1 RTP Features
        2. 6.22.9.2 Timing Specifications
      10. 6.22.10 Data Modification Module (DMM)
        1. 6.22.10.1 DMM Features
        2. 6.22.10.2 Timing Specifications
      11. 6.22.11 Boundary Scan Chain
  7. 7 Peripheral Information and Electrical Specifications
    1. 7.1  Enhanced Translator PWM Modules (ePWM)
      1. 7.1.1 ePWM Clocking and Reset
      2. 7.1.2 Synchronization of ePWMx Time-Base Counters
      3. 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.1.5 ePWM Synchronization with External Devices
      6. 7.1.6 ePWM Trip Zones
        1. 7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.1.6.2 Trip Zone TZ4n
        3. 7.1.6.3 Trip Zone TZ5n
        4. 7.1.6.4 Trip Zone TZ6n
      7. 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Electrical Data/Timing
    2. 7.2  Enhanced Capture Modules (eCAP)
      1. 7.2.1 Clock Enable Control for eCAPx Modules
      2. 7.2.2 PWM Output Capability of eCAPx
      3. 7.2.3 Input Connection to eCAPx Modules
      4. 7.2.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    3. 7.3  Enhanced Quadrature Encoder (eQEP)
      1. 7.3.1 Clock Enable Control for eQEPx Modules
      2. 7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.3.3 Input Connection to eQEPx Modules
      4. 7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 7.4  12-bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 7.4.1 MibADC Features
      2. 7.4.2 Event Trigger Options
        1. 7.4.2.1 MibADC1 Event Trigger Hookup
        2. 7.4.2.2 MibADC2 Event Trigger Hookup
        3. 7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.4.3 ADC Electrical and Timing Specifications
      4. 7.4.4 Performance (Accuracy) Specifications
        1. 7.4.4.1 MibADC Nonlinearity Errors
        2. 7.4.4.2 MibADC Total Error
    5. 7.5  General-Purpose Input/Output
      1. 7.5.1 Features
    6. 7.6  Enhanced High-End Timer (N2HET)
      1. 7.6.1 Features
      2. 7.6.2 N2HET RAM Organization
      3. 7.6.3 Input Timing Specifications
      4. 7.6.4 N2HET1-N2HET2 Interconnections
      5. 7.6.5 N2HET Checking
        1. 7.6.5.1 Internal Monitoring
        2. 7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 7.6.6 Disabling N2HET Outputs
      7. 7.6.7 High-End Timer Transfer Unit (HET-TU)
        1. 7.6.7.1 Features
        2. 7.6.7.2 Trigger Connections
    7. 7.7  Controller Area Network (DCAN)
      1. 7.7.1 Features
      2. 7.7.2 Electrical and Timing Specifications
    8. 7.8  Local Interconnect Network Interface (LIN)
      1. 7.8.1 LIN Features
    9. 7.9  Serial Communication Interface (SCI)
      1. 7.9.1 Features
    10. 7.10 Inter-Integrated Circuit (I2C)
      1. 7.10.1 Features
      2. 7.10.2 I2C I/O Timing Specifications
    11. 7.11 Multibuffered / Standard Serial Peripheral Interface
      1. 7.11.1 Features
      2. 7.11.2 MibSPI Transmit and Receive RAM Organization
      3. 7.11.3 MibSPI Transmit Trigger Events
        1. 7.11.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.11.3.2 MIBSPI2 Event Trigger Hookup
        3. 7.11.3.3 MIBSPI3 Event Trigger Hookup
        4. 7.11.3.4 MIBSPI4 Event Trigger Hookup
        5. 7.11.3.5 MIBSPI5 Event Trigger Hookup
      4. 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.11.5 SPI Slave Mode I/O Timings
    12. 7.12 Ethernet Media Access Controller
      1. 7.12.1 Ethernet MII Electrical and Timing Specifications
      2. 7.12.2 Ethernet RMII Timing
      3. 7.12.3 Management Data Input/Output (MDIO)
  8. 8 Applications, Implementation, and Layout
    1. 8.1 TI Design or Reference Design
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
      2. 9.1.2 Device and Development-Support Tool Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation from Texas Instruments
      2. 9.2.2 Receiving Notification of Documentation Updates
      3. 9.2.3 Community Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
    6. 9.6 Device Identification
      1. 9.6.1 Device Identification Code Register
      2. 9.6.2 Die Identification Registers
    7. 9.7 Module Certifications
      1. 9.7.1 DCAN Certification
      2. 9.7.2 LIN Certification
        1. 9.7.2.1 LIN Master Mode
        2. 9.7.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 9.7.2.3 LIN Slave Mode - Adaptive Baud Rate
  10. 10Mechanical Data
    1. 10.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZWT|337
サーマルパッド・メカニカル・データ
発注情報

1 Device Overview

1.1 Features

  • High-Performance Microcontroller for Safety-Critical Applications
    • Dual-Core Lockstep CPUs With ECC-Protected Caches
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU, High-End Timers, and On-Chip RAMs
    • Error Signaling Module (ESM) With Error Pin
    • Voltage and Clock Monitoring
  • ARM® Cortex® - R5F 32-Bit RISC CPU
    • 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single- and Double-Precision
    • 16-Region Memory Protection Unit (MPU)
    • 32KB of Instruction and 32KB of Data Caches With ECC
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • Up to 330-MHz CPU Clock
    • Core Supply Voltage (VCC): 1.14 to 1.32 V
    • I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
  • Integrated Memory
    • 4MB of Program Flash With ECC
    • 512KB of RAM With ECC
    • 128KB of Data Flash for Emulated EEPROM With ECC
  • 16-Bit External Memory Interface (EMIF)
  • Hercules™ Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt (RTI) Timer (OS Timer)
    • Two 128-Channel Vectored Interrupt Modules (VIMs) With ECC Protection on Vector Table
      • VIM1 and VIM2 in Safety Lockstep Mode
    • Two 2-Channel Cyclic Redundancy Checker (CRC) Modules
  • Direct Memory Access (DMA) Controller
    • 32 Channels and 48 Peripheral Requests
    • ECC Protection for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
  • Separate Nonmodulating PLL
  • IEEE 1149.1 JTAG, Boundary Scan, and ARM CoreSight™ Components
  • Advanced JTAG Security Module (AJSM) 
  • Trace and Calibration Capabilities
    • ETM™, RTP, DMM, POM
  • Multiple Communication Interfaces
    • 10/100 Mbps Ethernet MAC (EMAC)
      • IEEE 802.3 Compliant (3.3-V I/O Only)
      • Supports MII, RMII, and MDIO
    • Four CAN Controller (DCAN) Modules
      • 64 Mailboxes, Each With ECC Protection
      • Compliant to CAN Protocol Version 2.0B
    • Two Inter-Integrated Circuit (I2C) Modules
    • Five Multibuffered Serial Peripheral Interface (MibSPI) Modules
      • MibSPI1: 256 Words With ECC Protection
      • Other MibSPIs: 128 Words With ECC Protection
    • Four UART (SCI) Interfaces, Two With Local Interconnect Network (LIN 2.1) Interface Support
  • Two Next Generation High-End Timer (N2HET) Modules
    • 32 Programmable Channels Each
    • 256-Word Instruction RAM With Parity
    • Hardware Angle Generator for Each N2HET
    • Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET
  • Two 12-Bit Multibuffered Analog-to-Digital Converter (MibADC) Modules
    • MibADC1: 32 Channels Plus Control for up to 1024 Off-Chip Channels
    • MibADC2: 25 Channels
    • 16 Shared Channels
    • 64 Result Buffers Each With Parity Protection
  • Enhanced Timing Peripherals
    • 7 Enhanced Pulse Width Modulator (ePWM) Modules
    • 6 Enhanced Capture (eCAP) Modules
    • 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Three On-Die Temperature Sensors
  • Up to 145 Pins Available for General-Purpose I/O (GPIO)
  • 16 Dedicated GPIO Pins With External Interrupt Capability
  • Packages
    • 337-Ball Grid Array (ZWT) [Green]

1.2 Applications

  • Industrial Safety Applications
    • Industrial Automation
    • Industrial Motor Drives
    • Safe Programmable Logic Controllers (PLCs)
    • Power Generation and Distribution
    • Turbines and Windmills
    • Elevators and Escalators

1.3 Description

The RM57L843 device is part of the Hercules RM series of high-performance ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the development of IEC 61508 functional safety applications. Start evaluating today with the Hercules RM57x LaunchPad Development Kit. The RM57L843 device has on-chip diagnostic features including: dual CPUs in lockstep, Built-In Self-Test (BIST) logic for CPU, the N2HET coprocessors, and for on-chip SRAMs; ECC protection on the L1 caches, L2 flash, and SRAM memories. The device also supports ECC or parity protection on peripheral memories and loopback capability on peripheral I/Os.

The RM57L843 device integrates two ARM Cortex-R5F floating-point CPUs, operating in lockstep, which offer an efficient 1.66 DMIPS/MHz, and can run up to 330 MHz providing up to 547 DMIPS. The device supports the little-endian [LE] format.

The RM57L843 device has 4MB of integrated flash and 512KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory, implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (the same level as the I/O supply) for all read, program, and erase operations. The SRAM supports read and write accesses in byte, halfword, and word modes.

The RM57L843 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors with up to 64 total I/O terminals.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information or drive actuators with complex and accurate time pulses. The High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The Enhanced Pulse Width Modulator (ePWM) module can generate complex pulse width waveforms with minimal CPU overhead or intervention. The ePWM is easy to use and supports both high-side and low-side PWM and deadband generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM is ideal for digital motor control applications.

The Enhanced Capture (eCAP) module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or for simple PWM generation when not needed for capture applications.

The Enhanced Quadrature Encoder Pulse (eQEP) module directly interfaces with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems.

The device has two 12-bit-resolution MibADCs with 41 total channels and 64 words of parity-protected buffer RAM. The MibADC channels can be converted individually or by group for special conversion sequences. Sixteen channels are shared between the two MibADCs. Each MibADC supports three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired. One of the channels in MibADC1 and two of the channels in MibADC2 can be used to convert temperature measurements from the three on-chip temperature sensors.

The device has multiple communication interfaces: Five MibSPIs; four UART (SCI) interfaces, two with LIN support; four CANs; two I2C modules; and one Ethernet controller. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard (LIN 2.1) and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The Ethernet module supports MII, RMII, and Management Data I/O (MDIO) interfaces. The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C module supports speeds of 100 and 400 kbps.

The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module multiplies the external frequency reference to a higher frequency for internal use. The Global Clock Module (GCM) manages the mapping between the available clock sources and the internal device clock domains.

The device also has two External Clock Prescaler (ECP) modules. When enabled, the ECPs output a continuous external clock on the ECLK1 and ECLK2 balls. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The Direct Memory Access (DMA) controller has 32 channels, 48 peripheral requests, and ECC protection on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors on-chip device errors and determines whether an interrupt or external Error pin/ball (nERROR) is triggered when a fault is detected. The nERROR signal can be monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous memories or other slave devices.

A Parameter Overlay Module (POM) is included to enhance the debugging capabilities of application code. The POM can reroute flash accesses to internal RAM or to the EMIF, thus avoiding the reprogramming steps necessary for parameter updates in flash. This capability is particularly helpful during real-time system calibration cycles.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built-in ARM Cortex-R5F CoreSight debug features, the Embedded Cross Trigger (ECT) supports the interaction and synchronization of multiple triggering events within the SoC. An External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or minimal impact on the program execution time of the application code.

With integrated safety features and a wide choice of communication and control peripherals, the RM57L843 device is an ideal solution for high-performance real-time control applications with safety-critical requirements.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
RM57L843ZWT NFBGA (337) 16.00 mm × 16.00 mm
(1) For more information on these devices, see Section 10, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

RM57L843 lockstep_catalog_RM_bd2.gif Figure 1-1 Functional Block Diagram