SPNS155I September   2009  – June 2015 SM470R1B1M-HT

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Characteristics
  4. 4 Bare Die
    1. 4.1 Bare Die Information
  5. 5 Pin Configuration and Functions
    1. 5.1 Features
    2. 5.2 Pin Functions (HFQ/HKP Package)
    3. 5.3 Pin Functions (PGE Package)
  6. 6  Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Electrical Characteristics
    5. 6.5  Thermal Characteristics
    6. 6.6  ZPLL and Clock Specifications
    7. 6.7  RST and PORRST Timings
    8. 6.8  JTAG Scan Interface Timing
    9. 6.9  Output Timings
    10. 6.10 Input Timings
    11. 6.11 Flash Timings
    12. 6.12 SPIn Master Mode Timing Parameters
    13. 6.13 SPIn Slave Mode Timing Parameters
    14. 6.14 SCIN Isosynchronous Mode Timings - Internal Clock
    15. 6.15 SCIN Isosynchronous Mode Timings - External Clock
    16. 6.16 I2C Timing
    17. 6.17 Standard Can Controller (SCC) Mode Timings
    18. 6.18 Expansion Bus Module Timing
    19. 6.19 Multi-Buffered A-to-D Converter (MibADC)
  7. 7 Parameter Measurement Information
    1. 7.1 External Reference Resonator/Crystal Oscillator Clock Option
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 MibADC
        1. 8.1.1.1 MibADC Event Trigger Enhancements
      2. 8.1.2 JTAG Interface
      3. 8.1.3 High-End Timer (HET) Timings
        1. 8.1.3.1 Minimum PWM Output Pulse Width
        2. 8.1.3.2 Minimum Input Pulses that can be Captured
      4. 8.1.4 Interrupt Priority (IEM to CIM)
      5. 8.1.5 Expansion Bus Module (EBM)
    2. 8.2 Memory
      1. 8.2.1 Memory Selects
        1. 8.2.1.1 JTAG Security Module
        2. 8.2.1.2 Memory Security Module
        3. 8.2.1.3 RAM
        4. 8.2.1.4 F05 Flash
          1. 8.2.1.4.1 Flash Protection Keys
          2. 8.2.1.4.2 Flash Read
          3. 8.2.1.4.3 Flash Pipeline Mode
          4. 8.2.1.4.4 Flash Program and Erase
          5. 8.2.1.4.5 HET RAM
          6. 8.2.1.4.6 Peripheral Selects and Base Addresses
          7. 8.2.1.4.7 Direct-Memory Access (DMA)
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Identification Code Register
      2. 9.1.2 Timing Parameter Symbology
    2. 9.2 Development Support
    3. 9.3 Device Nomenclature
    4. 9.4 Documentation Support
    5. 9.5 Community Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Device Characteristics

CHARACTERISTICS(1) DEVICE DESCRIPTION SM470R1B1M COMMENTS
MEMORY
For the number of memory selects on this device, see Table 8-5, SM470R1B1M Memory Selection Assignment.
INTERNAL MEMORY Pipeline/non-pipeline


1MB flash
64KB SRAM


MSM
JTAG security module		 Flash is pipeline-capable.


The B1M RAM is implemented in one 64K array selected by two memory-select signals (see Table 8-5, SM470R1B1M Memory Selection Assignment ).
PERIPHERALS
For the device-specific interrupt priority configurations, see Table 8-2, Interrupt Priority. And for the 1K peripheral address ranges and their peripheral selects, see Table 8-7, B1M Peripherals, System Module, and Flash Base Addresses.
CLOCK ZPLL Zero-pin PLL has no external loop filter pins.
Expansion bus EBM Expansion bus module with 42 pins. Supports 8- and 16-bit memories. See Table 8-3 for details.
GENERAL-PURPOSE I/Os 46 I/O Port A has 8 external pins.
Port B has only 1 external pin.
Port C has 5 external pins.
Port D has 6 external pins.
Ports E, F, and G each have 8 external pins.
Port H has 2 external pins.
ECP Yes
SCI 3 (3 pin)
CAN (HECC and/or SCC) 2 HECC Two HECC
SPI (5-pin, 4-pin, or 3-pin) 2 (5 pin)
I2C 5
HET with XOR share 12 I/O The high-resolution (HR) SHARE feature allows even-numbered HR pins to share the next higher odd-numbered HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. For more information on HR SHARE, see the TMS470R1x High-End Timer (HET) Reference Guide (SPNU199).
HET RAM 64-instruction capacity
MibADC 10-bit, 12-channel
64-word FIFO		 Both the logic and registers for a full 16-channel MibADC are present.
CORE VOLTAGE 1.8 V
I/O VOLTAGE 3.3 V
PINS 84 or 144
PACKAGES HFQ, HKP, or PGE
(1) This table identifies all the characteristics of the B1M device except the SYSTEM and CPU, which are generic.