3 Pin Configuration and Functions

Figure 3-1 SN54AC74 J or W Package; SN74AC74 D, DB, N, NS, or PW Package (Top View)

Figure 3-2 SN54AC74 FK Package (Top View)

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
1 CLR	1	Input	Channel 1, Clear Input, Active Low
1D	2	Input	Channel 1, Data Input
1CLK	3	Input	Channel 1, Positive edge triggered clock input
1 PRE	4	Input	Channel 1, Preset Input, Active Low
1Q	5	Output	Channel 1, Output
1 Q	6	Output	Channel 1, Inverted Output
GND	7	—	Ground
2 Q	8	Output	Channel 2, Inverted Output
2Q	9	Output	Channel 2, Output
2 PRE	10	Input	Channel 2, Preset Input, Active Low
2CLK	11	Input	Channel 2, Positive edge triggered clock input
2D	12	Input	Channel 2, Data Input
2 CLR	13	Input	Channel 2, Clear Input, Active Low
V_CC	14	—	Positive Supply

(1) Signal Types: I = Input, O = Output, I/O = Input or Output