SCLS115G December   1982  – September 2015 SN54HC164 , SN74HC164

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, TA = 25°C
    6. 7.6  Electrical Characteristics, TA = -55°C to 125°C
    7. 7.7  Electrical Characteristics, TA = -55°C to 85°C
    8. 7.8  Timing Requirements, TA = 25°C
    9. 7.9  Timing Requirements, TA = -55°C to 125°C
    10. 7.10 Timing Requirements, TA = -55°C to 85°C
    11. 7.11 Switching Characteristics, TA = 25°C
    12. 7.12 Switching Characteristics, TA = -55°C to 125°C
    13. 7.13 Switching Characteristics, TA = -55°C to 85°C
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

9 Detailed Description

9.1 Overview

The SN74HC164 is an 8-bit shift register with 2 serial inputs (A and B) connected through an AND gate, as well as an asynchronous clear (CLR). The device requires a high signal on both A and B in order to set the input data line high; a low signal on either input will set the input data line low. Data at A and B can be changed while CLK is high or low, provided that the minimum set-up time requirements are met.

The CLK pin of the SN74HC164 is triggered on a positive or rising-edge signal, from LOW to HIGH. Upon a positive-edge trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The data of the last register, QH, will be discarded at each clock trigger. If a low signal is applied to the CLR pin of the SN74HC164, the device will set all registers to a value of 0 immediately.

9.2 Functional Block Diagram

SN54HC164 SN74HC164 Logic_1.gif

9.3 Feature Description

The HC164 has a wide operating voltage range of 2 V to 6 V, outputs that can drive up to 10 LSTTL loads and Low Power Consumption, 80-μA maximum I. It is typically tpd = 20 ns and has ±4-mA output drive at 5 V with low input current of 1-μA maximum. It also has AND-gated (enable/disable) serial inputs a fully buffered clock and serial inputs as well as a direct clear.

9.4 Device Functional Modes

Table 1 lists the functional modes of the SNx4HC164.

Table 1. Function Table(1)(2)

INPUTS OUTPUTS
CLR CLK A B QA QB . . . QH
L X X X L L L
H L X X QA0 QB0 QH0
H ↑ H H H QAn QGn
H ↑ L X L QAn QGn
H ↑ X L L QAn QGn
(1) QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established.
(2) QAn, QGn = the level of QA or QG before the most recent ↑ transition of CLK: indicates a 1-bit shift.