JAJSLW6F December   1982  – April 2021 SN54HC32 , SN74HC32

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information - 74
    5. 6.5  Thermal Information - 54
    6. 6.6  Electrical Characteristics - 74
    7. 6.7  Electrical Characteristics - 54
    8. 6.8  Switching Characteristics - 74
    9. 6.9  Switching Characteristics - 54
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
      1.      Application and Implementation
        1. 9.1 Application Information
        2. 9.2 Typical Application
          1. 9.2.1 Design Requirements
            1. 9.2.1.1 Power Considerations
            2. 9.2.1.2 Input Considerations
            3. 9.2.1.3 Output Considerations
          2. 9.2.2 Detailed Design Procedure
          3. 9.2.3 Application Curves
            1.         Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Overview

This device contains four independent 2-input OR gates. Each gate performs the Boolean function Y = A + B in positive logic.