JAJSMD1F December   1982  – June 2021 SN54HC74 , SN74HC74

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - 74
    6. 6.6  Electrical Characteristics - 54
    7. 6.7  Timing Requirements - 74
    8. 6.8  Timing Requirements - 54
    9. 6.9  Switching Characteristics - 74
    10. 6.10 Switching Characteristics - 54
    11. 6.11 Operating Characteristics
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
        4. 9.2.1.4 Timing Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-B11D1586-D1E1-4042-9D17-D5500C669E34.html#GUID-B11D1586-D1E1-4042-9D17-D5500C669E34. The worst case resistance is calculated with the maximum input voltage, given in the GUID-4854D19B-9DC3-4F29-8E22-0C3EA2F8F634.html#GUID-4854D19B-9DC3-4F29-8E22-0C3EA2F8F634, and the maximum input leakage current, given in the GUID-B11D1586-D1E1-4042-9D17-D5500C669E34.html#GUID-B11D1586-D1E1-4042-9D17-D5500C669E34, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-82E9E3E2-777C-45E2-92CF-04B6272268FA.html#GUID-82E9E3E2-777C-45E2-92CF-04B6272268FA to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.