9.2.1 Design Requirements

This device uses CMOS technology. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. Parallel output drive can create fast edges into light loads, so consider routing and load conditions to prevent ringing.

9.2.2 Detailed Design Procedure

This circuit is designed around an RC network that produces a slow input to the second inverter. The RC time constant (τ) is calculated from: τ = RC.

The delay time for this circuit is from t_delay(min) = –ln |1 – V_T+(min) / V_CC| τ to t_delay(max) = –ln |1 – V_T+(max) / V_CC| τ. It must be noted that the delay is consistent for each device, but because the switching threshold is only ensured between the minimum and maximum value, the output pulse length varies between devices. These values must be calculated by using the minimum and maximum ensured V_T+ values in the Electrical Characteristics.

The resistor value must be chosen such that the maximum current to and from the SNx414/SNx4LS14 is 8 mA at
5-V V_CC.

9.2.3 Application Curve

Figure 29. Ideal Capacitor Voltage and Output Voltage With Positive Switching Threshold