SDLS144D April   1985  – October 2016 SN54LS240 , SN54LS241 , SN54LS244 , SN54S240 , SN54S241 , SN54S244 , SN74LS240 , SN74LS241 , SN74LS244 , SN74S240 , SN74S241 , SN74S244

 

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - SNx4LS24x
    6. 6.6 Electrical Characteristics - SNx4S24x
    7. 6.7 Switching Characteristics - SNx4LS24x
    8. 6.8 Switching Characteristics - SNx4S24x
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 SN54LS24x and SN74LS24x Devices
    2. 7.2 SN54S24x and SN74S24x Devices
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 3-State Outputs
      2. 8.3.2 PNP Inputs
      3. 8.3.3 Hysteresis on Bus Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

7.1 SN54LS24x and SN74LS24x Devices

SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_1_01_sdls144.gif Figure 2. Load Circuit,
For 2-State Totem-Pole Outputs
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_1_02_sdls144.gif Figure 3. Load Circuit,
For Open-Collector Outputs
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_1_03_sdls144.gif Figure 4. Load Circuit,
For 3-State Outputs
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_1_04_sdls144.gif Figure 5. Voltage Waveforms,
Pulse Durations
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_1_05_sdls144.gif Figure 6. Voltage Waveforms,
Setup and Hold Times
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_1_06_sdls144.gif Figure 7. Voltage Waveforms,
Propagation Delay Times
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_1_07_sdls144.gif
A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO is approximately
50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
Figure 8. Voltage Waveforms,
Enable and Disable Times, 3-State Outputs

7.2 SN54S24x and SN74S24x Devices

SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_01_sdls144.gif Figure 9. Load Circuit,
For 2-State Totem-Pole Outputs
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_02_sdls144.gif Figure 10. Load Circuit,
For Open-Collector Outputs
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_03_sdls144.gif Figure 11. Load Circuit,
For 3-State Outputs
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_04_sdls144.gif Figure 12. Voltage Waveforms,
Pulse Durations
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_05_sdls144.gif Figure 13. Voltage Waveforms,
Setup and Hold Times
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_06_sdls144.gif Figure 14. Voltage Waveforms,
Propagation Delay Times
SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244 pmi_07_sdls144.gif
A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO is approximately
50 Ω; tr and tf ≤ 7 ns for SN54LS24x and SN74LS24x devices, and tr and tf ≤ 2.5 ns for SN54S24x and SN74S24x devices.
F. The outputs are measured one at a time with one input transition per measurement.
Figure 15. Voltage Waveforms,
Enable and Disable Times, 3-State Outputs