JAJST35V January   1993  – May 2024 SN54LVC74A , SN74LVC74A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information: SN74LVC74A
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: SN54LVC74A
    7. 5.7  Timing Requirements: SN74LVC74A
    8. 5.8  Timing Requirements: SN74LVC74A, –40°C to 125°C and –40°C to 85°C
    9. 5.9  Switching Characteristics: SN54LVC74A
    10. 5.10 Switching Characteristics: SN74LVC74A
    11. 5.11 Switching Characteristics: SN74LVC74A, –40°C to 125°C and –40°C to 85°C
    12. 5.12 Operating Characteristics
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • W|14
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

SN54LVC74A SN74LVC74A D, DB, J, PW, NS, or W Package14-Pin SOIC, SSOP, CDIP, TSSOP, SO, or CFP(Top View)Figure 4-1 D, DB, J, PW, NS, or W Package14-Pin SOIC, SSOP, CDIP, TSSOP, SO, or CFP(Top View)
SN54LVC74A SN74LVC74A FK Package20-Pin LCCC(Top View)Figure 4-3 FK Package20-Pin LCCC(Top View)
SN54LVC74A SN74LVC74A BQA or RGY Package14-Pin WQFN or VQFN With Exposed Thermal Pad(Top View)Figure 4-2 BQA or RGY Package14-Pin WQFN or VQFN With Exposed Thermal Pad(Top View)
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME CDIP, CFP, PDIP, SO, SOIC, SSOP, TSSOP, VQFN LCCC
1CLK 3 4 I Channel 1 clock input
1 CLR 1 2 I Channel 1 clear input. Pull low to set Q output low.
1D 2 3 I Channel 1 data input
1 PRE 4 6 I Channel 1 preset input. Pull low to set Q output high.
1Q 5 8 O Channel 1 output
1 Q 6 9 O Channel 1 inverted output
2CLK 11 16 I Channel 2 clock input
2 CLR 13 19 I Channel 2 clear input. Pull low to set Q output low.
2D 12 18 I Channel 2 data input
2 PRE 10 14 I Channel 2 preset input. Pull low to set Q output high.
2Q 9 13 O Channel 2 output
2 Q 8 12 O Channel 2 Inverted output
GND 7 10 — Ground
NC — 1, 5, 7, 11, 15, 17 — No connect
VCC 14 20 — Supply