JAJSSZ6C March   2007  – February 2024 SN65C1167E , SN65C1168E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Driver Output and Receiver Input ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Driver Section Electrical Characteristics
    6. 5.6 Receiver Section Electrical Characteristics
    7. 5.7 Driver Section Switching Characteristics
    8. 5.8 Receiver Section Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Active High Driver Output Enables
      2. 7.3.2 Active Low Receiver Enables
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Active Low Receiver Enables

Both SN65C1167E receivers can be configured with the single RE logic input. Receiver logic outputs are set at high-impedance when disabled.