JAJSPA1I June   1999  – October 2022 SN65C3243 , SN75C3243

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics, Driver Section
    7. 6.7  Electrical Characteristics, Receiver Section
    8. 6.8  Electrical Characteristics, Auto-Powerdown Section
    9. 6.9  Switching Characteristics: Driver
    10. 6.10 Switching Characteristics: Receiver
    11. 6.11 Switching Characteristics: Auto-Powerdown
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Device Functional Modes
      1. 8.2.1 Function Tables
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.10 Switching Characteristics: Receiver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS(3)TYP(1)UNIT
tPLHPropagation delay time, low- to high-level outputCL = 150 pF, See Figure 7-3150ns
tPHLPropagation delay time, high- to low-level outputCL = 150 pF, See Figure 7-3150ns
tenOutput enable timeCL = 150 pF, RL = 3 kΩ, See Figure 7-4200ns
tdisOutput disable timeCL = 150 pF, RL = 3 kΩ, See Figure 7-4200ns
tsk(p)Pulse skew(2)See Figure 7-350ns
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
(3) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.