JAJSFO2I september 2012 – october 2020 SN65DSI83
PRODUCTION DATA
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
A_CLKN | F9 | LVDS output | FlatLink Channel A LVDS clock |
A_CLKP | F8 | ||
ADDR | A1 | CMOS I/O | Local I2C Interface Target Address Select. See Table 7-3. In normal operation, this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI83 VCC 1.8-V power rail is connected. |
A_Y0N | C9 | LVDS output | FlatLink Channel A LVDS data output 0 |
A_Y0P | C8 | ||
A_Y1N | D9 | FlatLink Channel A LVDS data output 1 | |
A_Y1P | D8 | ||
A_Y2N | E9 | FlatLink Channel A LVDS data output 2 | |
A_Y2P | E8 | ||
A_Y3N | G9 | FlatLink Channel A LVDS data output 3. A_Y3P and A_Y3N shall be left NC for 18 bpp panels | |
A_Y3P | G8 | ||
DA0N | J3 | LVDS Input (HS) CMOS Input (LS) (failsafe) |
MIPI D-PHY Channel A Data Lane 0; data rate up to 1 Gbps |
DA0P | H3 | ||
DA1N | J4 | MIPI D-PHY Channel A Data Lane 1; data rate up to 1 Gbps | |
DA1P | H4 | ||
DA2N | J6 | MIPI D-PHY Channel A Data Lane 2; data rate up to 1 Gbps | |
DA2P | H6 | ||
DA3N | J7 | MIPI D-PHY Channel A Data Lane 3; data rate up to 1 Gbps | |
DA3P | H7 | ||
DACN | J5 | MIPI D-PHY Channel A Clock Lane; operates up to 500 MHz | |
DACP | H5 | ||
EN | B1 | CMOS Input with pullup (failsafe) | Chip enable and reset. Device is reset (shutdown) when EN is low. |
GND | A2, A8, B9, D5, E4, F4, F5, H9 | Power Supply | Reference ground |
IRQ | J9 | CMOS Output | Interrupt signal |
NC | B3, A3, B4, A4, B5, A5, B6, A6, B7, A7, C2, C1, D2, D1, F2, F1, G2, G1, E2, E1 | No connects | These pins must not be connected to any signal, power or ground. |
REFCLK | H2 | CMOS Input (Failsafe) | Optional external reference clock for LVDS pixel clock. If an external reference clock is not used, this pin must be pulled to GND with an external resistor. The source of the reference clock must be placed as close as possible with a series resistor near the source to reduce EMI. |
RSVD1 | H8 | CMOS Input/Output with pulldown | Reserved. This pin must be left unconnected for normal operation. |
RSVD2 | B2 | CMOS Input with pulldown | Reserved. This pin must be left unconnected for normal operation. |
SCL | H1 | CMOS Input (Failsafe) | Local I2C interface clock |
SDA | J1 | Open Drain I/O (failsafe) | Local I2C interface bidirectional data signal |
VCC | A9, B8, D6, E5, E6, F6, J2 | Power Supply | 1.8-V power supply |
VCORE | J8 | 1.1-V output from voltage regulator. This pin must have a 1-µF external capacitor to GND. |