JAJSFO2I september   2012  – october 2020 SN65DSI83

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-BDB96F65-5C5F-4805-AA4B-B71B15ADA38F/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  13.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
VILLow-level control signal input voltage0.3 × VCCV
VIHHigh-level control signal input voltage0.7 × VCC
VOHHigh-level output voltageIOH = –4 mA1.25
VOLLow-level output voltageIOL = 4 mA0.4
ILKGInput failsafe leakage currentVCC = 0; VCC(PIN) = 1.8 V±30μA
IIHHigh-level input currentAny input pin±30
IILLow-level input current
IOZHigh-impedance output currentAny output pin±10
IOSShort-circuit output currentAny output driving GND short±20mA
ICCDevice active currentSee (2)77112mA
IULPSDevice standby currentAll data and clock lanes are in ultra-low power state (ULPS)7.710
IRSTShutdown currentEN = 00.040.06
RENEN control input resistor200kΩ
MIPI DSI INTERFACE
VIH-LPLP receiver input high thresholdSee Figure 6-2880mV
VIL-LPLP receiver input low threshold550
|VID|HS differential input voltage70270
|VIDT|HS differential input voltage threshold50
VIL-ULPSLP receiver input low threshold; ultra-low power state (ULPS)300
VCM-HSHS common mode voltage; steady-state70330
ΔVCM-HSHS common mode peak-to-peak variation including symbol delta and interference100
VIH-HSHS single-ended input high voltageSee Figure 6-2460
VIL-HSHS single-ended input low voltage–40
VTERM-ENHS termination enable; single-ended input voltage (both Dp and Dn apply to enable)Termination is switched simultaneous for Dn and Dp450
RDIFF-HSHS mode differential input impedance80125Ω
FlatLink LVDS OUTPUT
|VOD|Steady-state differential output voltage for
A_Y x P/N and B_Y x P/N		CSR 0x19.3:2 = 00
100-Ω near-end termination		180245313mV
CSR 0x19.3:2 = 01
100-Ω near-end termination		215293372
CSR 0x19.3:2 = 10
100-Ω near-end termination		250341430
CSR 0x19.3:2 = 11
100-Ω near-end termination		290389488
CSR 0x19.3:2 = 00
200-Ω near-end termination		150204261
CSR 0x19.3:2 = 01
200-Ω near-end termination		200271346
CSR 0x19.3:2 = 10
200-Ω near-end termination		250337428
CSR 0x19.3:2 = 11
200-Ω near-end termination		300402511
Steady-state differential output voltage for
A_CLKP/N and B_CLKP/N		CSR 0x19.3:2 = 00
100-Ω near-end termination		140191244mV
CSR 0x19.3:2 = 01
100-Ω near-end termination		168229290
CSR 0x19.3:2 = 01
100-Ω near-end termination		195266335
CSR 0x19.3:2 = 11
100-Ω near-end termination		226303381
CSR 0x19.3:2 = 00
200-Ω near-end termination		117159204
CSR 0x19.3:2 = 01
200-Ω near-end termination		156211270
CSR 0x19.3:2 = 10
200-Ω near-end termination		195263334
CSR 0x19.3:2 = 11
200-Ω near-end termination		234314399
Δ|VOD|Change in steady-state differential output voltage between opposite binary statesRL = 100 Ω35mV
VOC(SS)Steady state common-mode output voltage (3)CSR 0x19.6 = 1 and CSR 0x1B.6 = 1
(see Figure 6-3)		0.80.91V
CSR 0x19.6 = 0 (see Figure 6-3)1.151.251.35
VOC(PP)Peak-to-peak common-mode output voltageSee Figure 6-335mV
RLVDS_DISPulldown resistance for disabled LVDS outputs1kΩ
(1) All typical values are at VCC = 1.8 V and TA = 25°C.
(2) SN65DSI83: SINGLE Channel DSI to SINGLE Channel DSI, 1280 × 800
  • Number of LVDS lanes = 3 data lanes + 1 CLK lane
  • Number of DSI lanes = 4 data lanes + 1 CLK lane
  • LVDS CLK OUT = 83 M
  • DSI CLK = 500 M
  • RGB888, LVDS 18 bpp
Maximum values are at VCC = 1.95 V and TA = 85°C
(3) Tested at VCC = 1.8 V , TA = –40°C for MIN, TA = 25°C for TYP, TA = 85°C for max.