JAJSFO2I september   2012  – october 2020 SN65DSI83

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-BDB96F65-5C5F-4805-AA4B-B71B15ADA38F/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  13.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1 Design Requirements

Table 8-1 Design Parameters
DESIGN PARAMETERSEXAMPLE VALUE
VCC1.8 V (±5%)
Clock Source (REFCLK or DSIA_CLK)DSIA_CLK
REFCKL FrequencyN/A
DSIA Clock Frequency500 MHz
PANEL INFORMATION
Pixel Clock (MHz)83 MHz
Horizontal Active (pixels)1280
Horizontal Blanking (pixels)384
Vertical Active (lines)800
Vertical Blanking (lines)30
Horizontal Sync Offset (pixels)64
Horizontal Sync Pulse Width (pixels)128
Vertical Sync Offset (lines)3
Vertical Sync Pulse Width (lines)7
PANEL INFORMATION (continued)
Horizontal Sync Pulse PolarityNegative
Vertical Sync Pulse PolarityNegative
Color Bit Depth (6 bpc or 8 bpc)6-bit
Number of LVDS Lanes1 × [3 Data Lanes + 1 Clock Lane]
DSI INFORMATION
Number of DSI Lanes1 × [4 Data Lanes + 1 Clock Lane]
DSI Clock Frequency(MHz)500 MHz
Dual DSI Configuration(Odd/Even or Left/Right)N/A