JAJSFO2I september   2012  – october 2020 SN65DSI83

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-BDB96F65-5C5F-4805-AA4B-B71B15ADA38F/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  13.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedure

The video resolution parameters required by the panel need to be programmed into the SN65DSI83 device. For this example, the parameters programmed would be the following:

 

Horizontal Active = 1280 or 0x500

CHA_ACTIVE_LINE_LENGTH_LOW = 0x00

CHA_ACTIVE_LINE_LENGTH_HIGH = 0x05

 

Vertical Active = 800 or 0x320

CHA_VERTICAL_DISPLAY_SIZE_LOW = 0x20

CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0x03

 

Horizontal Pulse Width = 128 or 0x80

CHA_HSYNC_PULSE_WIDTH_LOW = 0x80

CHA_HSYNC_PULSE_WIDTH_HIGH = 0x00

 

Vertical Pulse Width = 7

CHA_VSYNC_PULSE_WIDTH_LOW = 0x07

CHA_VSYNC_PULSE_WIDTH_HIGH = 0x00

 

Horizontal Backporch = HorizontalBlanking – (HorizontalSyncOffset + HorizontalSyncPulseWidth)

Horizontal Backporch = 384 – (64 + 128)

Horizontal Backporch = 192 or 0xC0

CHA_HORIZONTAL_BACK_PORCH = 0xC0

 

Vertical Backporch = VerticalBlanking – (VerticalSyncOffset +VerticalSyncPulseWidth)

Vertical Backporch = 30 – (3 + 7)

Vertical Backporch = 20 or 0x14

CHA_VERTICAL_BACK_PORCH = 0x14

 

Horizontal Frontporch = HorizontalSyncOffset

Horizontal Frontporch = 64 or 0x40

CHA_HORIZONTAL_FRONT_PORCH = 0x40

 

Vertical Frontporch = VerticalSyncOffset

Vertical Frontporch = 3

CHA_VERTICAL_FRONT_PORCH = 0x03

 

The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C and configuring the TEST PATTERN GENERATION PURPOSE ONLY register as shown in Table 7-8.

LVDS clock is derived from the DSI channel A clock. When the MIPI D-PHY channel A HS clock is used as the LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLink LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency range of the FlatLink LVDS output clock and DSI Channel A input clock respectively for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) must be set to enable the internal PLL.

LVDS_CLK_RANGE = 2 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz

HS_CLK_SRC = 1 – LVDS pixel clock derived from MIPI D-PHY channel A

DSI_CLK_DIVIDER = 00101 – Divide by 6

CHA_DSI_LANES = 00 – Four lanes are enabled

CHA_DSI_CLK_RANGE = 0x64 – 500 MHz