JAJSCS2B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x1A is shown in Figure 29 and described in Table 18.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | EVEN_ODD_SWAP | CHA_REVERSE_LVDS | CHB_REVERSE_LVDS | Reserved | CHA_LVDS_TERM | CHB_LVDS_TERM | |
R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-1 |
LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
BIT | FIELD | TYPE | RESET | DESCRIPTION | |
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7 | Reserved | Reserved | |||
6 | EVEN_ODD_SWAP | R/W | 0 | Note: When the SN65DSI85-Q1 device is in two stream mode (CSR 0x10.6:5 = 10), setting this bit to 1 causes the video stream from DSI Channel A to be routed to LVDS channel B and the video stream from DSI Channel B to be routed to LVDS channel A.
0: Odd pixels routed to LVDS Channel A and Even pixels routed to LVDS channel B (default) 1: Odd pixels routed to LVDS Channel B and Even pixels routed to LVDS channel A |
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5 | CHA_REVERSE_LVDS | R/W | 0 | This bit controls the order of the LVDS pins for channel A.
0: Normal LVDS Channel A pin order. LVDS channel A pin order is the same as listed in the Pin Configuration and Functions section. (default) 1: Reversed LVDS Channel A pin order. LVDS channel A pin order is remapped as follows:
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4 | CHB_REVERSE_LVDS | R/W | 0 | This bit controls the order of the LVDS pins for channel B.
0: Normal LVDS channel B pin order. LVDS channel B pin order is the same as listed in the Pin Configuration and Functions section. (default) 1: Reversed LVDS channel B pin order. LVDS channel B pin order is remapped as follows:
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3-2 | Reserved | Reserved | |||
1 | CHA_LVDS_TERM | R/W | 1 | This bit controls the near end differential termination for LVDS channel A. This bit also affects the output voltage for LVDS channel A.
0: 100-Ω differential termination 1: 200-Ω differential termination (default) |
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0 | CHB_LVDS_TERM | R/W | 1 | This bit controls the near end differential termination for LVDS channel B. This bit also affects the output voltage for LVDS channel B.
0: 100-Ω differential termination 1: 200-Ω differential termination (default) |