JAJSCS2B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x34 is shown in Figure 51 and described in Table 40.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHA_HORIZONTAL_BACK_PORCH | |||||||
R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7-0 | CHA_HORIZONTAL_BACK_PORCH | R/W | 0 | This field controls the time in pixel clocks between the end of the HSync Pulse and the start of the active video data for LVDS Channel A in single LVDS Channel mode (CSR 0x18.4 = 1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4 = 0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). |