JAJSCS2B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x3D is shown in Figure 60 and described in Table 49.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RIGHT_CROP | |||||||
R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7-0 | RIGHT_CROP | R/W | 0 | This field controls the number of pixels removed from the beginning of the active video line for DSI Channel B.
This field only has meaning if LEFT_RIGHT_PIXELS = 1. This field defaults to 0x00. Note: When the SN65DSI85-Q1 device is configured for dual DSI inputs in Left/Right mode and this field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied. |