JAJSCS2B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0xE0 is shown in Figure 62 and described in Table 51.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | IRQ_EN | ||||||
R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7-1 | Reserved | Reserved | ||
0 | IRQ_EN | R/W | 0 | When enabled by this field, the IRQ output is driven high to communicate IRQ events.
0: IRQ output is high-impedance (default) 1: IRQ output is driven high when a bit is set in registers 0xE5 or 0xE6 that also has the corresponding IRQ_EN bit set to enable the interrupt condition |