JAJSCS2B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0xE5 is shown in Figure 65 and described in Table 54.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHA_SYNCH_ERR | CHA_CRC_ERR | CHA_UNC_ECC_ERR | CHA_COR_ECC_ERR | CHA_LLP_ERR | CHA_SOT_BIT_ERR | Reserved | PLL_UNLOCK |
| R/W1C-0 | R/W1C-0 | R/W1C-0 | R/W1C-0 | R/W1C-0 | R/W1C-0 | R/W1C-1 |
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | CHA_SYNCH_ERR | R/W1C | 0 | This bit is set when the DSI channel A packet processor detects an HS or VS synchronization error, that is, an unexpected sync packet).
This bit is cleared by writing a 1 value. |
| 6 | CHA_CRC_ERR | R/W1C | 0 | This bit is set when the DSI channel A packet processor detects a data stream CRC error.
This bit is cleared by writing a 1 value. |
| 5 | CHA_UNC_ECC_ERR | R/W1C | 0 | This bit is set when the DSI channel A packet processor detects an uncorrectable ECC error.
This bit is cleared by writing a 1 value. |
| 4 | CHA_COR_ECC_ERR | R/W1C | 0 | This bit is set when the DSI channel A packet processor detects a correctable ECC error.
This bit is cleared by writing a 1 value. |
| 3 | CHA_LLP_ERR | R/W1C | 0 | This bit is set when the DSI channel A packet processor detects a low level protocol error.
This bit is cleared by writing a 1 value. Low level protocol errors include SoT and EoT sync errors, Escape Mode entry command errors, LP transmission sync errors, and false control errors. Lane merge errors are reported by this status condition. |
| 2 | CHA_SOT_BIT_ERR | R/W1C | 0 | This bit is set when the DSI channel A packet processor detects an SoT leader sequence bit error.
This bit is cleared by writing a 1 value. |
| 1 | Reserved | Reserved | ||
| 0 | PLL_UNLOCK | R/W1C | 1 | This bit is set whenever the PLL Lock status transitions from LOCK to UNLOCK. |