JAJSCS2B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Table 56 lists the design parameters for SN65DSI85-Q1.
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| VCC | 1.8 V (±5%) |
| CLOCK | DSIA_CLK |
| REFCKL Frequency | N/A |
| DSIA Clock Frequency | 490 MHz |
| PANEL INFORMATION | |
| LVDS Output Clock Frequency | 81 MHz |
| Resolution | 1920 × 1200 |
| Horizontal Active (pixels) | 960 |
| Horizontal Blanking (pixels) | 144 |
| Vertical Active (Lines) | 1200 |
| Vertical Blanking (lines) | 20 |
| Horizontal Sync Offset (pixels) | 50 |
| Horizontal Sync Pulse Width (pixels) | 50 |
| Vertical Sync Offset (lines) | 1 |
| Vertical Sync Pulse Width (lines) | 5 |
| Horizontal Sync Pulse Polarity | Negative |
| Vertical Sync Pulse Polarity | Negative |
| Color Bit Depth (6 bpc or 8 bpc) | 6-bit |
| Number of LVDS Lanes | 2 × [3 Data lanes + 1 Clock lane] |
| DSI INFORMATION | |
| Number of DSI Lanes | 1 × [4 Data Lanes + 1 Clock Lane] |
| DSI Input Clock Frequency | 490 MHz |
| Dual DSI Configuration (Odd/Even or Left/Right) | N/A |