JAJSFO0G september   2012  – october 2020 SN65DSI85

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-24B27461-2407-4A70-B6CA-5D1E4961612D/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8.   Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 24
      3. 7.4.3 Reset Implementation
      4. 7.4.4 Initialization Sequence
      5. 7.4.5 LVDS Output Formats
      6. 7.4.6 DSI Lane Merging
      7. 7.4.7 DSI Pixel Stream Packets
      8. 7.4.8 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Typical WUXGA 18-bpp Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Script
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Typical WQXGA 24-bpp Application
        1. 8.2.2.1 Design Requirements
  11. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  12. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.5 LVDS Output Formats

The SN65DSI85 processes DSI packets and produces video data driven to the FlatLink™ LVDS interface in an industry standard format. Single-Link LVDS and Dual-Link LVDS are supported by the SN65DSI85; when the FlatLink™ output is implemented in a Dual-Link configuration, channel A carries the odd pixel data, and channel B carries the even pixel data. During conditions such as the default condition, and some video synchronization periods, where no video stream data is passing from the DSI input to the LVDS output, the SN65DSI85 transmits zero value pixel data on the LVDS outputs while maintaining transmission of the vertical sync and horizontal sync status.

Figure 7-4 illustrates a Single-Link LVDS 18 bpp application.

Figure 7-5 illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are transferred on the Y3P/N LVDS lane.

Figure 7-6 illustrates a 24 bpp Single-Link application using Format 1. In data Format 1, the two LSB per color are transferred on the Y3P/N LVDS lane.

Figure 7-7 illustrates a Single-Link LVDS application where 24 bpp data is received from DSI and converted to 18 bpp data for transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to 1 and CHA_24BPP_MODE (CSR 0x18.3) to 0. In this configuration, the SN65DSI85 will not transmit the 2 LSB per color since the Y3P/N LVDS lane is disabled.

Note:

Note: Figure 7-4, Figure 7-5, Figure 7-6, and Figure 7-7 only illustrate a few example applications for the SN65DSI85. Other applications are also supported.

GUID-9313336B-0C9C-4923-9981-E131D0FDE356-low.gif
DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low
Figure 7-4 FlatLink™ Output Data; Single-Link 18 bpp
GUID-C1A4A6B7-0EB2-4BAA-BC59-181FE57C27B6-low.gif
DE = Data Enable; (o) = Odd Pixels; (e) = Even Pixels
Figure 7-5 FlatLink™ Output Data (Format 2); Dual-Link 24 bpp
GUID-6AED005D-D860-4E82-B33F-670AEDE43E1E-low.gif
DE = Data Enable; Channel B Clock and Data are Output Low
Figure 7-6 FlatLink™ Output Data (Format 1); Single-Link 24 bpp
GUID-57F8B523-E336-435D-9540-860B84938A29-low.gif
DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low
Figure 7-7 FlatLink™ Output Data (Format 1); 24 bpp to Single-Link 18 bpp Conversion