JAJSFO0G september   2012  – october 2020 SN65DSI85

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-24B27461-2407-4A70-B6CA-5D1E4961612D/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8.   Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 24
      3. 7.4.3 Reset Implementation
      4. 7.4.4 Initialization Sequence
      5. 7.4.5 LVDS Output Formats
      6. 7.4.6 DSI Lane Merging
      7. 7.4.7 DSI Pixel Stream Packets
      8. 7.4.8 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Typical WUXGA 18-bpp Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Script
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Typical WQXGA 24-bpp Application
        1. 8.2.2.1 Design Requirements
  11. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  12. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.4 Initialization Sequence

Use the following initialization sequence to setup the SN65DSI85. This sequence is required for proper operation of the device. Steps 9 through 11 in the sequence are optional.

Table 7-5 Initialization Sequence
INITIALIZATION SEQUENCE NUMBERINITIALIZATION SEQUENCE DESCRIPTION
Init seq 1Power on
Init seq 2After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven to LP11 state
Init seq 3Set EN pin to Low
Wait 10 ms (1)
Init seq 4Tie EN pin to High
Wait 10 ms (1)
Init seq 5Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI8x is not functional until the CSR registers are initialized)
Init seq 6Set the PLL_EN bit (CSR 0x0D.0)
Wait 10 ms (1)
Init seq 7Set the SOFT_RESET bit (CSR 0x09.0)
Wait 10 ms (1)
Init seq 8Change DSI data lanes to HS state and start DSI video stream
Wait 5 ms (1)
Init seq 9Read back all resisters and confirm they were correctly written
Init seq 10Write 0xFF to CSR 0xE5 and CSR 0xE6 to clear the error registers
Wait 1 ms (1)
Init seq 11Read CSR 0xE5 and CSR 0xE6. If CSR 0xE5 and CSR 0xE6 != 0x00, then go back to step #2 and re-initialize
(1) Minimum recommended delay. It is fine to exceed these.