SLLS753E February 2007 – September 2016 SN65HVD1040-Q1
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The SN65HVD1040-Q1 CAN bus transceiver meets or exceeds the ISO 11898 standard as a high-speed controller area network (CAN) bus physical layer device. The device is designed to interface between the differential bus lines in controller area network and the CAN protocol controller at data rates up to 1 Mbps.
Select the high-speed mode of the device operation by setting the STB pin low. The CAN bus driver and receiver are fully operational and the CAN communication is bidirectional. The driver is translating a digital input on TXD to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD.
If a high logic level is applied to the STB pin, the device enters a low-power bus-monitor standby mode. While the SN65HVD1040-Q1 is in the low-power bus-monitor standby mode, a dominant bit greater than 5 µs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may then reactivate the device when it needs to transmit to the bus.
During normal mode, the mode where the CAN driver is active, the TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware or software failure where TXD is held dominant longer than the time-out period tTXD_DTO. The DTO circuit is triggered on a falling edge on the driver input, TXD. The DTO circuit disables the CAN bus driver if no rising edge is seen on TXD before the time-out period expires. This frees the CAN bus for communication between other nodes on the network. The CAN driver is re-enabled when a rising edge is seen on the driver input, TXD, thus clearing the TXD DTO condition. The receiver and RXD pin still reflect the CAN bus, and the bus pins are biased to recessive level during a TXD DTO.
NOTE
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data rate on the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate. Calculate the minimum transmitted data rate using: Minimum Data Rate = 11 / tTXD_DTO.
The SN65HVD1040-Q1 device has a thermal shutdown that turns off the driver outputs when the junction temperature nears 190°C. This shutdown prevents catastrophic failure from bus shorts, but does not protect the circuit from possible damage. The user should strive to maintain recommended operating conditions, and not exceed absolute maximum ratings at all times. If the SN65HVD1040-Q1 device is subjected to many or long durations faults that can put the device into thermal shutdown, it must be replaced.
A reference voltage (VCC/2) is available through the SPLIT output pin. The SPLIT voltage must be tied to the common-mode point in a split termination network, hence the pin name, to help stabilize the output common-mode voltage. See Figure 28 for more application specific information on properly terminating the CAN bus.
The SN65HVD1040-Q1 is characterized for operation from –40°C to 125°C.
Table 2 and Table 3 lists the functional modes of the SN65HVD1040-Q1.
INPUTS | OUTPUTS | BUS STATE | ||
---|---|---|---|---|
TXD | STB | CANH | CANL | |
L | L | H | L | Dominant |
H | L | Z | Z | Recessive |
Open | L | Z | Z | Recessive |
X | H or Open | Y | Y | Recessive |
DIFFERENTIAL INPUTS VID = V(CANH) – V(CANL) |
STB | OUTPUT RXD |
BUS STATE |
---|---|---|---|
VID ≥ 0.9 V | L | L | Dominant |
VID ≥ 1.15 V | H or Open | L | Dominant |
0.5 V < VID < 0.9 V | X | ? | ? |
VID ≤ 0.5 V | X | H | Recessive |
Open | X | H | Recessive |
TJA1040(1) | PARAMETER | HVD10xx |
---|---|---|
TJA1040 DRIVER SECTION | ||
VIH | High-level input voltage | Recommended VIH |
VIL | Low-level input voltage | Recommended VIL |
IIH | High-level input current | Driver IIH |
IIL | Low-level input current | Driver IIL |
TJA1040 BUS SECTION | ||
Vth(dif) | Differential input voltage | Receiver VIT and recommended VID |
Vhys(dif) | Differential input hysteresis | Receiver Vhys |
VO(dom) | Dominant output voltage | Driver VO(D) |
VO(reces) | Recessive output voltage | Driver VO(R) |
VI(dif)(th) | Differential input voltage | Receiver VIT and recommended VID |
VO(dif0(bus) | Differential bus voltage | Driver VOD(D) and VOD(R) |
ILI | Power-off bus input current | Receiver II(off) |
IO(SC) | Short-circuit output current | Driver IOS(SS) |
RI(cm) | CANH, CANL input resistance | Receiver RIN |
RI(def) | Differential input resistance | Receiver RID |
RI(cm) (m) | Input resistance matching | Receiver RI (m) |
CI(cm) | Input capacitance to ground | Receiver CI |
CI(dif) | Differential input capacitance | Receiver CID |
TJA1040 RECEIVER SECTION | ||
IOH | High-level output current | Recommended IOH |
IOL | Low-level output current | Recommended IOL |
TJA1040 SPLIT PIN SECTION | ||
VO | Reference output voltage | VO |
TJA1040 TIMING SECTION | ||
td(TXD-BUSon) | Delay TXD to bus active | Driver tPLH |
td(TXD-BUSoff) | Delay TXD to bus inactive | Driver tPHL |
td(BUSon-RXD) | Delay bus active to RXD | Receiver tPHL |
td(BUSoff-RXD) | Delay bus inactive to RXD | Receiver tPLH |
tPD(TXD–RXD) | Prop delay TXD to RXD | Device tLOOP1 and tLOOP2 |
td(stb-norm) | Enable time from standby to dominant | Driver ten |
TJA1040 STB PIN SECTION | ||
VIH | High-level input voltage | Recommended VIH |
VIL | Low-level input voltage | Recommended VIL |
IIH | High-level input current | IIH |
IIL | Low-level input current | IIL |