SLLS632C December 2005 – February 2015 SN65HVD1050
PRODUCTION DATA.
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VCC | Supply voltage(2) | –0.3 | 7 | V | ||
Voltage range at any bus terminal (CANH, CANL, Vref) | –27 | 40 | V | |||
IO | Receiver output current | 20 | mA | |||
VI | Voltage input, transient pulse(3) (CANH, CANL) | –200 | 200 | V | ||
VI | Voltage input range (TXD, S) | –0.5 | 6 | V | ||
TJ | Junction temperature | –55 | 170 | °C | ||
Tstg | Storage temperature | –40 | 125 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins | ±8000 | V |
Bus pins vs GND | ±4000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | ||||
Machine Model, ANSI/ESDS5.2-1996 | ±200 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
VCC | Supply voltage | 4.5 | 5.5 | V | |||
VI or VIC | Voltage at any bus terminal (separately or common mode) | –12 | 12 | V | |||
VIH | High-level input voltage | TXD, S | 2.1 | VCC | V | ||
VIL | Low-level input voltage | 0 | 0.8 | V | |||
VID | Differential input voltage | –7 | 7 | V | |||
IOH | High-level output current | Driver | –70 | mA | |||
Receiver | –2 | ||||||
IOL | Low-level output current | Driver | 70 | mA | |||
Receiver | 2 | ||||||
TJ | Junction temperature | See Absolute Maximum Ratings, 1-Mbps minimum signaling rate with RL = 54 Ω | –40 | 150 | °C | ||
Signaling Rate | 20 | kbps |
THERMAL METRIC(1) | SN65HVD1050 | UNIT | |
---|---|---|---|
D (SOIC) | |||
8 PINS | |||
RθJA | Junction-to-air, Low-K thermal resistance(2) | 211 | °C/W |
Junction-to-air, High-K thermal resistance | 131 | ||
RθJC(top) | Junction-to-case (top) thermal resistance | 79 | |
RθJB | Junction-to-board thermal resistance | 53 | |
ψJT | Junction-to-top characterization parameter | 10.3 | |
ψJB | Junction-to-board characterization parameter | 56.6 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 112 | |
PD | Average power dissipation, VCC = 5.0V, Tj = 27°C, RL = 60 Ω, S at 0V, Input to TXD a 500 kHz, 50% duty cycle square wave. CL at RXD = 15 pF | 170 | mW |
Average power dissipation, VCC = 5.5V, Tj = 130°C, RL = 45 Ω, S at 0V, Input to TXD a 500 kHz, 50% duty cycle square wave. CL at RXD = 15 pF | 170 | ||
TJ_shutdown | Junction temperature, thermal shutdown(3) | 190 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VO(D) | Bus output voltage (Dominant) | CANH | VI = 0V, S at 0V, RL = 60 Ω, See Figure 11 and Figure 12 | 4.75V < VCC < 5.25V | 2.9 | 3.4 | 4.5 | V |
4.5V < VCC < 5.5V | 2.75 | 5.2 | ||||||
CANL | 4.75V < VCC < 5.25V | 0.8 | 1.5 | |||||
4.5V < VCC < 5.5V | 1.6 | |||||||
VO(R) | Bus output voltage (Recessive) | VI = 3V, S at 0V, RL = 60 Ω, See Figure 11 and Figure 12 | 4.75V < VCC < 5.25V | 2 | 2.3 | 3 | V | |
4.5V < VCC < 5.5V | 1.8 | 3 | ||||||
VOD(D) | Differential output voltage (Dominant) | VI = 0V, RL = 60 Ω, S at 0V, See Figure 11, Figure 12, and Figure 13 | 4.75V < VCC < 5.25V | 1.5 | 3 | V | ||
4.5V < VCC < 5.5V | 1.4 | 3 | ||||||
VI = 0V, RL = 45 Ω, S at 0V, See Figure 11, Figure 12, and Figure 13 | 4.75V < VCC < 5.25V | 1.4 | 3 | |||||
4.5V < VCC < 5.5V | 1.3 | 3 | ||||||
VOD(R) | Differential output voltage (Recessive) | VI = 3V, S at 0V, See Figure 11 and Figure 12 | –0.012 | 0.012 | V | |||
VI = 3V, S at 0V, No Load | –0.5 | 0.05 | ||||||
VOC(ss) | Steady state common-mode output voltage | S at 0V, Figure 18 | 4.75V < VCC < 5.25V | 2 | 2.3 | 3 | V | |
4.5V < VCC < 5.5V | 1.9 | 3 | ||||||
ΔVOC(ss) | Change in steady-state common-mode output voltage | 30 | mV | |||||
IIH | High-level input current, TXD input | VI at VCC | –2 | 2 | μA | |||
IIL | Low-level input current, TXD input | VI at 0V | –50 | –10 | ||||
IO(off) | Power-off TXD output current | VCC at 0V, TXD at 5V | 1 | |||||
IOS(ss) | Short-circuit steady-state output current | VCANH = -12V, CANL Open, See Figure 21 | –105 | –72 | mA | |||
VCANH = 12V, CANL Open, SeeFigure 21 | 0.36 | 1 | ||||||
VCANL = -12V, CANH Open, See Figure 21 | –1 | –0.5 | ||||||
VCANL = 12V , CANH Open, See Figure 21 | 71 | 105 | ||||||
CO | Output capacitance | See receiver input capacitance |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VIT+ | Positive-going input threshold voltage | S at 0V, See Table 1 | 800 | 900 | mV | |||
VIT– | Negative-going input threshold voltage | 500 | 650 | |||||
Vhys | Hysteresis voltage (VIT+ – VIT–) | 100 | 125 | |||||
VOH | High-level output voltage | IO = –2 mA, See Figure 16 | 4.75V < VCC < 5.25V | 4 | 4.6 | V | ||
4.5V < VCC < 5.5V | 3.8 | |||||||
VOL | Low-level output voltage | IO = 2 mA, See Figure 16 | 0.2 | 0.4 | V | |||
II(off) | Power-off bus input current | CANH or CANL = 5V, Other pin at 0V, VCC at 0V, TXD at 0V |
165 | 250 | μA | |||
IO(off) | Power-off RXD leakage current | VCC at 0V, RXD at 5V | 20 | μA | ||||
CI | Input capacitance to ground, (CANH or CANL) | TXD at 3V, VI = 0.4 sin (4E6πt) + 2.5V |
13 | pF | ||||
CID | Differential input capacitance | TXD at 3V, VI = 0.4 sin (4E6πt) | 5 | |||||
RID | Differential input resistance | TXD at 3V, S at 0V | 30 | 80 | kΩ | |||
RIN | Input resistance, (CANH or CANL) | 15 | 30 | 40 | ||||
RI(m) | Input resistance matching [1 – (RIN (CANH) / RIN (CANL))] x 100% |
V(CANH) = V(CANL) | –3% | 0% | 3% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
td(LOOP1) | Total loop delay, driver input to receiver output, recessive to dominant | Figure 19, S at 0V | 4.75V < VCC < 5.25V | 90 | 190 | ns | |
4.5V < VCC < 5.5V | 85 | 195 | |||||
td(LOOP2) | Total loop delay, driver input to receiver output, dominant to recessive | 4.75V < VCC < 5.25V | 90 | 190 | |||
4.5V < VCC < 5.5V | 85 | 195 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH | Propagation delay time, low-to-high-level output | S at 0V, See Figure 14 | 25 | 65 | 120 | ns | |
tPHL | Propagation delay time, high-to-low-level output | 25 | 45 | 90 | |||
tr | Differential output signal rise time | 25 | |||||
tf | Differential output signal fall time | 50 | |||||
ten | Enable time from silent mode to dominant | See Figure 17 | 1 | μs | |||
t(dom) | Dominant time-out | ↓VI, See Figure 20 | 4.75V < VCC < 5.25V | 300 | 450 | 700 | μs |
4.5V < VCC < 5.5V | 280 | 700 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH | Propagation delay time, low-to-high-level output | S at 0V or VCC, See Figure 16 | 4.75V < VCC < 5.25V | 60 | 100 | 130 | ns |
4.5V < VCC < 5.5V | 60 | 135 | |||||
tPHL | Propagation delay time, high-to-low-level output | 4.75V < VCC < 5.25V | 45 | 70 | 90 | ||
4.5V < VCC < 5.5V | 45 | 95 | |||||
tr | Output signal rise time | 8 | |||||
tf | Output signal fall time | 8 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ICC | 5-V Supply current | Silent mode | S at VCC, VI = VCC | 6 | 10 | mA | ||
Dominant | VI = 0V, 60 Ω Load, S at 0V | 4.75V < VCC < 5.25V | 50 | 70 | ||||
4.5V < VCC < 5.5V | 75 | |||||||
Recessive | VI = VCC, No Load, S at 0V | 6 | 10 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IIH | High level input current | S at 2V | 20 | 40 | 70 | μA |
IIL | Low level input current | S at 0.8V | 5 | 20 | 30 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VREF | Reference output voltage | –50 μA < IO < 50 μA | 0.4VCC | 0.5VCC | 0.6VCC | V |