JAJSH83E June   2014  – April 2019 SN65HVD1470 , SN65HVD1471 , SN65HVD1473 , SN65HVD1474 , SN65HVD1476 , SN65HVD1477

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions — SOIC-8 and MSOP-8
    2.     Pin Functions — MSOP–10
    3.     Pin Functions — SOIC-14
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information — D Packages
    5. 7.5  Thermal Information — DGS and DGK Packages
    6. 7.6  Power Dissipation
    7. 7.7  Electrical Characteristics
    8. 7.8  Switching Characteristics — 400 kbps
    9. 7.9  Switching Characteristics — 20 Mbps
    10. 7.10 Switching Characteristics — 50 Mbps
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Equivalent Circuits
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1.      Master Enable Control
      2.      Slave Enable Control
      3. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
        5. 10.2.1.5 Transient Protection
      4. 10.2.2 Detailed Design Procedure
      5. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.1.4 Receiver Failsafe

The differential receivers of the SN65HVD147x family are failsafe to invalid bus states caused by the following:

  • Open bus conditions, such as a disconnected connector
  • Shorted bus conditions, such as cable damage shorting the twisted-pair together
  • Idle bus conditions that occur when no driver on the bus is actively driving

In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the receiver is not indeterminate.

Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than 200 mV, and must output a Low when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+, VIT–, and Vhys (the separation between VIT+ and VIT–). As shown in the Electrical Characteristics table, differential signals more negative than –200 mV will always cause a low receiver output, and differential signals more positive than 200 mV will always cause a high receiver output.

When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output will be High. Only when the differential input is more than Vhys below VIT+ will the receiver output transition to a Low state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver hysteresis value, Vhys, as well as the value of VIT+.

SN65HVD1470 SN65HVD1471 SN65HVD1473 SN65HVD1474 SN65HVD1476 SN65HVD1477 noise_immunity_sllsej8.gifFigure 33. SN65HVD147x Noise Immunity Under Bus Fault Conditions