JAJSV27E September   2010  – October 2024 SN65HVD1780-Q1 , SN65HVD1781-Q1 , SN65HVD1782-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings—AEC
    3. 5.3  ESD Ratings—IEC
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Power Dissipation Ratings
    8. 5.8  Switching Characteristics
    9. 5.9  Package Dissipation Ratings
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bus Fault Conditions
      2. 7.3.2 Receiver Failsafe
      3. 7.3.3 Hot-Plugging
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Bus Loading
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stub Length
        2. 8.2.2.2 Receiver Failsafe
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.8 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DRIVER (SN65HVD1780)
tr, tfDriver differential output rise/fall timeRL = 54 Ω,
CL = 50 pF,
See Figure 6-3		3.15 V < VCC < 3.45 V0.41.41.8μs
3.15 V < VCC < 5.5 V0.41.72.6µs
tPHL, tPLHDriver propagation delayRL = 54 Ω, CL = 50 pF, See Figure 6-30.82μs
tSK(P)Driver differential output pulse skew,
|tPHL – tPLH|		RL = 54 Ω, CL = 50 pF, See Figure 6-320250ns
tPHZ, tPLZDriver disable timeSee Figure 6-4 and Figure 6-50.15μs
tPZH, tPZLDriver enable timeReceiver enabledSee Figure 6-4 and Figure 6-50.23μs
Receiver disabled312
DRIVER (SN65HVD1781)
tr, tfDriver differential output rise/fall timeRL = 54 Ω, CL = 50 pF, See Figure 6-350300ns
tPHL, tPLHDriver propagation delayRL = 54 Ω, CL = 50 pF, See Figure 6-3200ns
tSK(P)Driver differential output pulse skew,
|tPHL – tPLH|		RL = 54 Ω, CL = 50 pF, See Figure 6-325ns
tPHZ, tPLZDriver disable timeSee Figure 6-4 and Figure 6-53μs
tPZH, tPZLDriver enable timeReceiver enabledSee Figure 6-4 and Figure 6-5300ns
Receiver disabled10μs
DRIVER (SN65HVD1782)
tr, tfDriver differential output rise/fall timeRL = 54 Ω,
CL = 50 pF		All VCC and Temp50ns
VCC > 4.5V and T < 105°C16
tPHL, tPLHDriver propagation delayRL = 54 Ω, CL = 50 pF, See Figure 6-355ns
tSK(P)Driver differential output pulse skew,
|tPHL – tPLH|		RL = 54 Ω, CL = 50 pF, See Figure 6-310ns
tPHZ, tPLZDriver disable timeSee Figure 6-4 and Figure 6-53μs
tPZH, tPZLDriver enable timeReceiver enabledSee Figure 6-4 and Figure 6-5300ns
Receiver disabled9μs
RECEIVER (ALL DEVICES UNLESS OTHERWISE NOTED)
tr, tfReceiver output rise/fall time (1)CL = 15 pF,
See Figure 6-6		All devices415ns
tPHL, tPLHReceiver propagation delay timeCL = 15 pF,
See Figure 6-6		HVD1780-Q1,
HVD1781-Q1		100200ns
HVD1782-Q180
tSK(P)Receiver output pulse skew,
|tPHL – tPLH|		CL = 15 pF,
See Figure 6-6		HVD1780-Q1,
HVD1781-Q1		620ns
HVD1782-Q15
tPLZ, tPHZReceiver disable time (1)Driver enabled, See Figure 6-715100ns
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)		Receiver enable timeDriver enabled, See Figure 6-780300ns
Driver disabled, See Figure 6-839μs
(1) Specified by design. Not production tested.