JAJSV27E September   2010  – October 2024 SN65HVD1780-Q1 , SN65HVD1781-Q1 , SN65HVD1782-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings—AEC
    3. 5.3  ESD Ratings—IEC
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Power Dissipation Ratings
    8. 5.8  Switching Characteristics
    9. 5.9  Package Dissipation Ratings
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bus Fault Conditions
      2. 7.3.2 Receiver Failsafe
      3. 7.3.3 Hot-Plugging
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Bus Loading
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stub Length
        2. 8.2.2.2 Receiver Failsafe
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1 Bus Fault Conditions

The SN65HVD178x-Q1 family of RS-485 transceivers is designed to survive bus pin faults up to ±70V. The SN65HVD1782-Q1 device will not survive a bus pin fault with a direct short to voltages above 30V when all of the following occurs:

  • The device is powered on
  • The driver is enabled (DE = HIGH), and one of the following is true
    • D = HIGH AND the bus fault is applied to the A pin
    • D = LOW AND the bus fault is applied to the B pin

Under other conditions, the device survives shorts to bus pin faults up to ±70V. Table 7-1 summarizes the conditions under which the device may be damaged, and the conditions under which the device will not be damaged.

Table 7-1 Bus Fault Conditions for the HVD1782
POWERDEDABRESULTS
OFFXX–70V < VA < 70V–70V < VB < 70VDevice survives
ONLOX–70V < VA < 70V–70V < VB < 70VDevice survives
ONHIL–70V < VA < 70V–70V < VB < 30VDevice survives
ONHIL–70V < VA < 70V30V < VBDamage may occur
ONHIH–70V < VA < 30V–70 V < VB < 30VDevice survives
ONHIH30V < VA–70V < VB < 30VDamage may occur