SLLS877H December   2007  – March 2017 SN65HVD1780 , SN65HVD1781 , SN65HVD1782

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings: JEDEC
    3. 7.3 ESD Ratings: IEC
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Power Dissipation Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Input Schematic
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 70-V Fault Protection
      2. 9.3.2 Receiver Failsafe
      3. 9.3.3 Hot-Plugging
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design with WEBENCH® Tools
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Custom Design with WEBENCH® Tools
      2. 13.1.2 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Detailed Description

9.1 Overview

The SN65HVD178x devices are half-duplex RS-485 transceivers available in three speed grades suitable for data transmission up to 115 kbps, 1 Mbps, and 10 Mbps.

These devices feature a wide common-mode operating range and bus-pin fault protection up to ±70 V. Each device has an active-HIGH driver enable and active-LOW receiver enable. A standby current of less than 1 µA can be achieved by disabling both driver and receiver.

9.2 Functional Block Diagram

SN65HVD1780 SN65HVD1781 SN65HVD1782 bd_slls877.gif

9.3 Feature Description

Internal ESD protection circuits protect the transceiver bus terminals against ±16 kV human body model (HBM) electrostatic discharges.

Device operation is specified over a wide temperature range from –40°C to 125°C.

9.3.1 70-V Fault Protection

The SN65HVD178x family of RS-485 transceivers is designed to survive bus pin faults up to ±70 V. The SN65HVD1782 will not survive a bus pin fault with a direct short to voltages above 30 V when:

  • The device is powered on, AND
  • The driver is enabled (DE = HIGH), AND
    • D = HIGH AND the bus fault is applied to the A pin, OR
    • D = LOW AND the bus fault is applied to the B pin

Under other conditions, the device will survive shorts to bus pin faults up to ±70 V. Table 1 summarizes the conditions under which the device may be damaged, and the conditions under which the device will not be damaged.

Table 1. Device Conditions

POWER DE D A B RESULTS
OFF X X –70 V < VA < 70 V –70 V < VB < 70 V Device survives
ON L X –70 V < VA < 70 V –70 V < VB < 70 V Device survives
ON H L –70 V < VA < 70 V –70 V < VB < 30 V Device survives
ON H L –70 V < VA < 70 V 30 V < VB Damage may occur
ON H H –70 V < VA < 30 V –70 V < VB < 30 V Device survives
ON H H 30 V < VA –70 V < VB < 30 V Damage may occur

9.3.2 Receiver Failsafe

The SN65HVD178x family of half-duplex transceivers provides internal biasing of the receiver input thresholds in combination with large input-threshold hysteresis. At a positive input threshold of VIT+ = –35 mV and an input hysteresis of VHYS = 30 mV, the receiver output remains logic high under bus-idle, bus-short, or open bus conditions in the presence of up to 130 mVPP differential noise without the need for external failsafe biasing resistors.

9.3.3 Hot-Plugging

These devices are designed to operate in "hot swap" or "hot pluggable" applications. Key features for hot-pluggable applications are power-up and power-down glitch-free operation, default disabled input and output pins, and receiver failsafe.

As shown in Figure 1, an internal power-on reset circuit keeps the driver outputs in a high-impedance state until the supply voltage has reached a level at which the device will reliably operate. This ensures that no problems will occur on the bus pin outputs as the power supply turns on or turns off.

As shown in Device Functional Modes, the enable inputs have the feature of default disable on both the driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R pin until the associated controller actively drives the enable pins.

9.4 Device Functional Modes

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is negative.

When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin has an internal pulldown resistor to ground, thus, when left open, the driver is disabled (high-impedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is enabled, output A turns high and B turns low.

Table 2. Driver Function Table

INPUT ENABLE OUTPUTS FUNCTION
D DE A B
H H H L Actively drive bus high
L H L H Actively drive bus low
X L Z Z Driver disabled (1)
X OPEN Z Z Driver disabled by default (1)
OPEN H H L Actively drive bus high by default


When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R, turns high. When VID is negative and lower than the negative input threshold, VIT-, the receiver output, R, turns low. If VID is between VIT+ and VIT- the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).

Table 3. Receiver Function Table

DIFFERENTIAL INPUT ENABLE OUTPUT FUNCTION
VID = VA – VB RE R
VIT+ < VID L H Receive valid bus high
VIT– < VID < VIT+ L ? Indeterminate bus state
VID < VIT– L L Receive valid bus low
X H Z Receiver disabled (1)
X OPEN Z Receiver disabled by default (1)
Open-circuit bus L H Fail-safe high output
Short-circuit bus L H Fail-safe high output
Idle (terminated) bus L H Fail-safe high output
(1) When both the driver and receiver are disabled, the device enters a low-power standby mode.