JAJS488J January 2008 – March 2023 SN65HVD1785 , SN65HVD1786 , SN65HVD1787 , SN65HVD1791 , SN65HVD1792 , SN65HVD1793
PRODUCTION DATA
The differential receiver of the SN75HVD17xx family is failsafe to invalid bus states caused by:
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the “input indeterminate” range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than +200 mV, and must output a low when VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are VIT(+) and VIT(-). As shown in the Electrical Characteristics table, differential signals more negative than -200 mV will always cause a low receiver output, and differential signals more positive than +200 mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of -10 mV, and the receiver output will be high.